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Mirror of https://github.com/cyring/CoreFreq
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develop
[x86_64] Version 1.97.2
CyrIng
26 hours
master
[x86_64] Version 1.97.2
CyrIng
26 hours
Tag
Download
Author
Age
1.97.1
commit 3a25d36977...
CyrIng
3 weeks
1.97.0
commit 93db56941e...
CyrIng
3 months
1.96.5
commit 150a2191f3...
CyrIng
10 months
1.96.4
commit 49fce8116b...
CyrIng
11 months
1.96.3
commit 706460f852...
CyrIng
11 months
1.96.2
commit bdd9400a86...
CyrIng
11 months
1.96.1
commit a28ea7bea3...
CyrIng
12 months
1.96.0
commit 11bdf0a545...
CyrIng
12 months
1.95.5
commit 34efe5d3e6...
CyrIng
14 months
1.95.4
commit 2e293e5102...
CyrIng
14 months
[...]
Age
Commit message
Author
26 hours
[x86_64] Version 1.97.2
HEAD
master
develop
CyrIng
2 days
[Intel] Prefetchers fix of L1 Scrubbing, L1 Next Page and L2 AMP
CyrIng
3 days
[Intel] EEO and R2H bits inversion fix in MSR_POWER_CTL (0x1fc)
CyrIng
5 days
[Intel] Reverse specification of MSR UNCORE_PERF_STATUS
CyrIng
12 days
[AMD][Phoenix] Adding the unlocked Ryzen 8000 Series
CyrIng
12 days
[AMD][Hawk Point] Adding Ryzen PRO processors
CyrIng
2024-04-05
Version 1.97.1
1.97.1
CyrIng
2024-04-05
[AMD][Ryzen] Adding the Embedded 7000 and 8000 Series
CyrIng
2024-04-05
[AMD] CPUID bits completeness
CyrIng
2024-04-03
[AMD][Ryzen] Adding other Rembrandt-R and Dragon Range processors
CyrIng
[...]
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