diff options
| author | CyrIng <labs@cyring.fr> | 2024-04-24 14:15:06 +0200 |
|---|---|---|
| committer | CyrIng <labs@cyring.fr> | 2024-04-24 14:15:06 +0200 |
| commit | bdd67e27448ab1b7b2be4b2fddd67a23dbecbee7 (patch) | |
| tree | 08cd0ad34f9babb78970fa70d682d405cef13480 | |
| parent | daa3e09e3f13a89e5934495280cc156c83b57291 (diff) | |
[Intel] Reverse specification of MSR UNCORE_PERF_STATUS
| -rw-r--r-- | x86_64/intel_reg.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/x86_64/intel_reg.h b/x86_64/intel_reg.h index 229d35d..bcda3e1 100644 --- a/x86_64/intel_reg.h +++ b/x86_64/intel_reg.h @@ -156,6 +156,7 @@ #define MSR_HSW_EP_UNCORE_PERF_FIXED_CTR_CTRL 0x00000703 #define MSR_HSW_UNCORE_RATIO_LIMIT 0x00000620 +#define MSR_HSW_UNCORE_PERF_STATUS 0x00000621 #ifndef MSR_CONFIG_TDP_NOMINAL #define MSR_CONFIG_TDP_NOMINAL 0x00000648 @@ -1652,7 +1653,7 @@ typedef union */ typedef union -{ /* 06_3D/06_3F/06_47/06_4F/06_55/06_56/06_57/06_66/06_85/06_8E/06_9E */ +{ /*[06_3C]/06_3D/06_3F/06_47/06_4F/06_55/06_56/06_57/06_66/06_85/06_8E/06_9E */ unsigned long long value; struct { @@ -1665,6 +1666,24 @@ typedef union } UNCORE_RATIO_LIMIT; typedef union +{ /* 06_3C/[06_3D]/06_3F/06_45/06_46/[06_47]/06_4F/06_55/[06_56]/06_57/06_8C */ + unsigned long long value; + struct + { + unsigned long long + CurrentRatio : 7-0, + ReservedBits1 : 16-7, + CurrentVID : 32-16, + ReservedBits2 : 64-32; + }; +} UNCORE_PERF_STATUS; +/* Tiger Lake/U [06_8C] CurrentVID / 8192 + Idle 0x182f001a -> 0.7557V + Stress 0x1b770023 -> 0.8582V + Turbo 0x1bf20024 -> 0.8732V +*/ + +typedef union { unsigned long long value; struct |