diff options
author | CyrIng <labs@cyring.fr> | 2023-06-11 12:01:08 +0200 |
---|---|---|
committer | CyrIng <cyril.ingenierie@gmail.com> | 2023-06-11 12:01:08 +0200 |
commit | 49fce8116b0e890aa14c7c1637ae645767247a19 (patch) | |
tree | 97ff0ff29b951374f1477567c0b0ccf34d88f183 | |
parent | 03318383aa2463f71c89253c902cc4d2fc597a22 (diff) |
[AMD64] Display CPUID state of new and legacy features:1.96.4
* Fused Multiply Add [FMA4]
* Extended Operation Support [XOP]
* Translation Cache Extension [TCE]
* Trailing Bit Manipulation [TBM]
* OS Visible Work-around [OSVW]
* LOCK prefix to read CR8 [AltMov]
-rw-r--r-- | corefreq-cli-rsc-en.h | 5 | ||||
-rw-r--r-- | corefreq-cli-rsc-fr.h | 5 | ||||
-rw-r--r-- | corefreq-cli-rsc.c | 5 | ||||
-rw-r--r-- | corefreq-cli-rsc.h | 5 | ||||
-rw-r--r-- | corefreq-cli.c | 55 |
5 files changed, 71 insertions, 4 deletions
diff --git a/corefreq-cli-rsc-en.h b/corefreq-cli-rsc-en.h index d2c19e4..f18e008 100644 --- a/corefreq-cli-rsc-en.h +++ b/corefreq-cli-rsc-en.h @@ -1085,6 +1085,7 @@ #define RSC_FEATURES_APIC_CODE_EN "Advanced Programmable Interrupt Controller" #define RSC_FEATURES_AVIC_CODE_EN "Advanced Virtual Interrupt Controller" #define RSC_FEATURES_ARAT_CODE_EN "APIC Timer Invariance" +#define RSC_FEATURES_ALTMOV_CODE_EN "LOCK prefix to read CR8" #define RSC_FEATURES_CLZERO_CODE_EN "Clear Zero Instruction" #define RSC_FEATURES_CORE_MP_CODE_EN "Core Multi-Processing" #define RSC_FEATURES_CNXT_ID_CODE_EN "L1 Data Cache Context ID" @@ -1125,6 +1126,7 @@ #define RSC_FEATURES_MTRR_CODE_EN "Memory Type Range Registers" #define RSC_FEATURES_NX_CODE_EN "No-Execute Page Protection" #define RSC_FEATURES_OSXSAVE_CODE_EN "OS-Enabled Ext. State Management" +#define RSC_FEATURES_OSVW_CODE_EN "OS Visible Work-around" #define RSC_FEATURES_PAE_CODE_EN "Physical Address Extension" #define RSC_FEATURES_PAT_CODE_EN "Page Attribute Table" #define RSC_FEATURES_PBE_CODE_EN "Pending Break Enable" @@ -1146,6 +1148,8 @@ #define RSC_FEATURES_SMAP_CODE_EN "Supervisor-Mode Access Prevention" #define RSC_FEATURES_SMEP_CODE_EN "Supervisor-Mode Execution Prevention" #define RSC_FEATURES_ITD_CODE_EN "Thread Director" +#define RSC_FEATURES_TBM_CODE_EN "Trailing Bit Manipulation" +#define RSC_FEATURES_TCE_CODE_EN "Translation Cache Extension" #define RSC_FEATURES_TSC_CODE_EN "Time Stamp Counter" #define RSC_FEATURES_TSC_DEADLN_CODE_EN "Time Stamp Counter Deadline" #define RSC_FEATURES_TSXABORT_CODE_EN "TSX Force Abort MSR Register" @@ -1159,6 +1163,7 @@ #define RSC_FEATURES_XD_BIT_CODE_EN "Execution Disable Bit Support" #define RSC_FEATURES_XSAVE_CODE_EN "XSAVE/XSTOR States" #define RSC_FEATURES_XTPR_CODE_EN "xTPR Update Control" +#define RSC_FEATURES_XOP_CODE_EN "Extended Operation Support" #define RSC_FEAT_SECTION_MECH_CODE_EN "Mitigation mechanisms" #define RSC_FEAT_SECTION_SEC_CODE_EN "Security Features" diff --git a/corefreq-cli-rsc-fr.h b/corefreq-cli-rsc-fr.h index d37aeb6..ebd462a 100644 --- a/corefreq-cli-rsc-fr.h +++ b/corefreq-cli-rsc-fr.h @@ -559,6 +559,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_APIC_CODE_FR "Advanced Programmable Interrupt Controller" #define RSC_FEATURES_AVIC_CODE_FR "Advanced Virtual Interrupt Controller" #define RSC_FEATURES_ARAT_CODE_FR "APIC Timer Invariance" +#define RSC_FEATURES_ALTMOV_CODE_FR "LOCK prefix to read CR8" #define RSC_FEATURES_CLZERO_CODE_FR "Clear Zero Instruction" #define RSC_FEATURES_CORE_MP_CODE_FR "Core Multi-Processing" #define RSC_FEATURES_CNXT_ID_CODE_FR "L1 Data Cache Context ID" @@ -599,6 +600,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_MTRR_CODE_FR "Memory Type Range Registers" #define RSC_FEATURES_NX_CODE_FR "No-Execute Page Protection" #define RSC_FEATURES_OSXSAVE_CODE_FR "OS-Enabled Ext. State Management" +#define RSC_FEATURES_OSVW_CODE_FR "OS Visible Work-around" #define RSC_FEATURES_PAE_CODE_FR "Physical Address Extension" #define RSC_FEATURES_PAT_CODE_FR "Page Attribute Table" #define RSC_FEATURES_PBE_CODE_FR "Pending Break Enable" @@ -620,6 +622,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_SMAP_CODE_FR "Supervisor-Mode Access Prevention" #define RSC_FEATURES_SMEP_CODE_FR "Supervisor-Mode Execution Prevention" #define RSC_FEATURES_ITD_CODE_FR "Thread Director" +#define RSC_FEATURES_TBM_CODE_FR "Trailing Bit Manipulation" +#define RSC_FEATURES_TCE_CODE_FR "Translation Cache Extension" #define RSC_FEATURES_TSC_CODE_FR "Time Stamp Counter" #define RSC_FEATURES_TSC_DEADLN_CODE_FR "Time Stamp Counter Deadline" #define RSC_FEATURES_TSXABORT_CODE_FR "TSX Force Abort MSR Register" @@ -633,6 +637,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo #define RSC_FEATURES_XD_BIT_CODE_FR "Execution Disable Bit Support" #define RSC_FEATURES_XSAVE_CODE_FR "XSAVE/XSTOR States" #define RSC_FEATURES_XTPR_CODE_FR "xTPR Update Control" +#define RSC_FEATURES_XOP_CODE_FR "Extended Operation Support" #define RSC_FEAT_SECTION_MECH_CODE_FR "M""\xa9""canismes d'att""\xa9""nuation" #define RSC_FEAT_SECTION_SEC_CODE_FR "Fonctions de s""\xa9""curit""\xa9" diff --git a/corefreq-cli-rsc.c b/corefreq-cli-rsc.c index 2266010..3fb4314 100644 --- a/corefreq-cli-rsc.c +++ b/corefreq-cli-rsc.c @@ -944,6 +944,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_APIC), LDT(RSC_FEATURES_AVIC), LDT(RSC_FEATURES_ARAT), + LDT(RSC_FEATURES_ALTMOV), LDT(RSC_FEATURES_CLZERO), LDT(RSC_FEATURES_CORE_MP), LDT(RSC_FEATURES_CNXT_ID), @@ -979,6 +980,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_MTRR), LDT(RSC_FEATURES_NX), LDT(RSC_FEATURES_OSXSAVE), + LDT(RSC_FEATURES_OSVW), LDT(RSC_FEATURES_PAE), LDT(RSC_FEATURES_PAT), LDT(RSC_FEATURES_PBE), @@ -1000,6 +1002,8 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_SMAP), LDT(RSC_FEATURES_SMEP), LDT(RSC_FEATURES_ITD), + LDT(RSC_FEATURES_TBM), + LDT(RSC_FEATURES_TCE), LDT(RSC_FEATURES_TSC), LDT(RSC_FEATURES_TSC_DEADLN), LDT(RSC_FEATURES_TSXABORT), @@ -1013,6 +1017,7 @@ RESOURCE_ST Resource[] = { LDT(RSC_FEATURES_XD_BIT), LDT(RSC_FEATURES_XSAVE), LDT(RSC_FEATURES_XTPR), + LDT(RSC_FEATURES_XOP), LDT(RSC_FEAT_SECTION_MECH), LDT(RSC_FEAT_SECTION_SEC), LDT(RSC_TECHNOLOGIES_TITLE), diff --git a/corefreq-cli-rsc.h b/corefreq-cli-rsc.h index 0792491..e91e67c 100644 --- a/corefreq-cli-rsc.h +++ b/corefreq-cli-rsc.h @@ -747,6 +747,7 @@ enum { RSC_FEATURES_APIC, RSC_FEATURES_AVIC, RSC_FEATURES_ARAT, + RSC_FEATURES_ALTMOV, RSC_FEATURES_CLZERO, RSC_FEATURES_CORE_MP, RSC_FEATURES_CNXT_ID, @@ -782,6 +783,7 @@ enum { RSC_FEATURES_MTRR, RSC_FEATURES_NX, RSC_FEATURES_OSXSAVE, + RSC_FEATURES_OSVW, RSC_FEATURES_PAE, RSC_FEATURES_PAT, RSC_FEATURES_PBE, @@ -803,6 +805,8 @@ enum { RSC_FEATURES_SMAP, RSC_FEATURES_SMEP, RSC_FEATURES_ITD, + RSC_FEATURES_TBM, + RSC_FEATURES_TCE, RSC_FEATURES_TSC, RSC_FEATURES_TSC_DEADLN, RSC_FEATURES_TSXABORT, @@ -816,6 +820,7 @@ enum { RSC_FEATURES_XD_BIT, RSC_FEATURES_XSAVE, RSC_FEATURES_XTPR, + RSC_FEATURES_XOP, RSC_FEAT_SECTION_MECH, RSC_FEAT_SECTION_SEC, RSC_TECHNOLOGIES_TITLE, diff --git a/corefreq-cli.c b/corefreq-cli.c index 66e5355..f352ce7 100644 --- a/corefreq-cli.c +++ b/corefreq-cli.c @@ -2362,6 +2362,14 @@ REASON_CODE SysInfoFeatures( Window *win, }, { (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.AltMov == 1, + attr_Feat, + 2, "%s%.*sAltMov [%7s]", RSC(FEATURES_ALTMOV).CODE(), + width - 21 - RSZ(FEATURES_ALTMOV), + NULL + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, RO(Shm)->Proc.Features.leaf80000008.EBX.CLZERO, attr_Feat, 2, "%s%.*sCLZERO [%7s]", RSC(FEATURES_CLZERO).CODE(), @@ -2474,12 +2482,19 @@ REASON_CODE SysInfoFeatures( Window *win, NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.FMA4 == 1, + attr_Feat, + 2, "%s%.*sFMA4 [%7s]", RSC(FEATURES_FMA).CODE(), + width - 19 - RSZ(FEATURES_FMA), + NULL + }, + { NULL, - (RO(Shm)->Proc.Features.Std.ECX.FMA == 1) - || (RO(Shm)->Proc.Features.ExtInfo.ECX.FMA4 == 1), + RO(Shm)->Proc.Features.Std.ECX.FMA == 1, attr_Feat, - 2, "%s%.*sFMA | FMA4 [%7s]", RSC(FEATURES_FMA).CODE(), - width - 25 - RSZ(FEATURES_FMA), + 2, "%s%.*sFMA [%7s]", RSC(FEATURES_FMA).CODE(), + width - 18 - RSZ(FEATURES_FMA), NULL }, { @@ -2643,6 +2658,14 @@ REASON_CODE SysInfoFeatures( Window *win, NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.OSVW == 1, + attr_Feat, + 2, "%s%.*sOSVW [%7s]", RSC(FEATURES_OSVW).CODE(), + width - 19 - RSZ(FEATURES_OSVW), + NULL + }, + { NULL, RO(Shm)->Proc.Features.Std.EDX.PAE == 1, attr_Feat, @@ -2813,6 +2836,22 @@ REASON_CODE SysInfoFeatures( Window *win, NULL }, { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.TBM == 1, + attr_Feat, + 2, "%s%.*sTBM [%7s]", RSC(FEATURES_TBM).CODE(), + width - 18 - RSZ(FEATURES_TBM), + NULL + }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.TCE == 1, + attr_Feat, + 2, "%s%.*sTCE [%7s]", RSC(FEATURES_TCE).CODE(), + width - 18 - RSZ(FEATURES_TCE), + NULL + }, + { NULL, RO(Shm)->Proc.Features.InvariantTSC, attr_TSC, @@ -2918,6 +2957,14 @@ REASON_CODE SysInfoFeatures( Window *win, width - 19 - RSZ(FEATURES_XTPR), NULL }, + { + (unsigned int[]) { CRC_AMD, CRC_HYGON, 0 }, + RO(Shm)->Proc.Features.ExtInfo.ECX.XOP == 1, + attr_Feat, + 2, "%s%.*sXOP [%7s]", RSC(FEATURES_XOP).CODE(), + width - 18 - RSZ(FEATURES_XOP), + NULL + }, /* Section Mark */ { NULL, |