[Intel] Prefetchers fix of L1 Scrubbing, L1 Next Page and L2 AMP

4 files changed, 94 insertions, 42 deletions

diff --git a/x86_64/corefreq-api.h b/x86_64/corefreq-api.h
index 78e9ea7..9502aff 100644
--- a/x86_64/corefreq-api.h
+++ b/x86_64/corefreq-api.h
@@ -898,7 +898,8 @@ typedef struct
 	BitCC			TM_Mask 	__attribute__ ((aligned (16)));
 	BitCC			ODCM_Mask	__attribute__ ((aligned (16)));
 	BitCC			DCU_Mask	__attribute__ ((aligned (16)));
-	BitCC			PCORE_Mask	__attribute__ ((aligned (16)));
+	BitCC			L1_Scrub_Mask	__attribute__ ((aligned (16)));
+	BitCC			L2_AMP_Mask	__attribute__ ((aligned (16)));
 	BitCC			ECORE_Mask	__attribute__ ((aligned (16)));
 	BitCC			PowerMgmt_Mask	__attribute__ ((aligned (16)));
 	BitCC			SpeedStep_Mask	__attribute__ ((aligned (16)));
diff --git a/x86_64/corefreqd.c b/x86_64/corefreqd.c
index f57c804..d147da8 100644
--- a/x86_64/corefreqd.c
+++ b/x86_64/corefreqd.c
@@ -1624,7 +1624,7 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
 
 	RO(Shm)->Proc.Technology.L1_Scrubbing = BITWISEAND_CC(LOCKLESS,
 						RW(Proc)->L1_Scrubbing,
-						RO(Proc)->PCORE_Mask) != 0;
+						RO(Proc)->L1_Scrub_Mask) != 0;
 
 	RO(Shm)->Proc.Technology.L2_HW_Prefetch = BITCMP_CC(LOCKLESS,
 						RW(Proc)->L2_HW_Prefetch,
@@ -1636,7 +1636,7 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
 
 	RO(Shm)->Proc.Technology.L2_AMP_Prefetch = BITWISEAND_CC(LOCKLESS,
 						RW(Proc)->L2_AMP_Prefetch,
-						RO(Proc)->PCORE_Mask) != 0;
+						RO(Proc)->L2_AMP_Mask) != 0;
 
 	RO(Shm)->Proc.Technology.L2_NLP_Prefetch = BITWISEAND_CC(LOCKLESS,
 						RW(Proc)->L2_NLP_Prefetch,
diff --git a/x86_64/corefreqk.c b/x86_64/corefreqk.c
index 60cc119..a40c6e6 100644
--- a/x86_64/corefreqk.c
+++ b/x86_64/corefreqk.c
@@ -9138,13 +9138,6 @@ static void Intel_DCU_Technology(CORE_RO *Core) 		/*Per Core */
 		ToggleFeature = 1;
 		break;
 	}
-	switch (L1_NPP_PREFETCH_Disable) {
-	case COREFREQ_TOGGLE_OFF:
-	case COREFREQ_TOGGLE_ON:
-		MiscFeatCtrl.L1_NPP_Prefetch = L1_NPP_PREFETCH_Disable;
-		ToggleFeature = 1;
-		break;
-	}
     if (ToggleFeature == 1)
     {
 	WRMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL);
@@ -9170,11 +9163,6 @@ static void Intel_DCU_Technology(CORE_RO *Core) 		/*Per Core */
     } else {
 	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch, Core->Bind);
     }
-    if (MiscFeatCtrl.L1_NPP_Prefetch == 1) {
-	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
-    } else {
-	BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
-    }
 	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask, Core->Bind);
 
     switch (Core->T.Cluster.Hybrid.CoreType) {
@@ -9227,18 +9215,9 @@ static void Intel_DCU_Technology(CORE_RO *Core) 		/*Per Core */
   }
 }
 
-static void Intel_Core_MicroArchitecture(CORE_RO *Core) 	/* Per P-Core */
-{ /* 06_7D, 06_7E, 06_8C, 06_8D, 06_97, 06_9A, 06_B7, 06_BA, 06_BF, MTL */
-  if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1))
-  {
-    switch (Core->T.Cluster.Hybrid.CoreType) {
-    case Hybrid_Atom:
-	/*	No MSR_CORE_UARCH_CTL(0x541) register with E-Core	*/
-	break;
-    case Hybrid_Core:
-      {
+static void Intel_Core_MicroArchControl(CORE_RO *Core)
+{
 	CORE_UARCH_CTL Core_Uarch_Ctl = {.value = 0};
-	MISC_FEATURE_CONTROL MiscFeatCtrl = {.value = 0};
 
 	RDMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL);
 
@@ -9255,6 +9234,20 @@ static void Intel_Core_MicroArchitecture(CORE_RO *Core) 	/* Per P-Core */
 	} else {
 		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing, Core->Bind);
 	}
+	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->L1_Scrub_Mask, Core->Bind);
+}
+
+static void Intel_Core_MicroArchitecture(CORE_RO *Core) 	/* Per P-Core */
+{ /* 06_7D, 06_7E, 06_8C, 06_8D, 06_97, 06_9A, 06_B7, 06_BA, 06_BF, MTL */
+  if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1))
+  {
+    switch (Core->T.Cluster.Hybrid.CoreType) {
+    case Hybrid_Atom:
+	/*	No MSR_CORE_UARCH_CTL(0x541) register with E-Core	*/
+	break;
+    case Hybrid_Core:
+      {
+	MISC_FEATURE_CONTROL MiscFeatCtrl = {.value = 0};
 
 	RDMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL);
 
@@ -9272,7 +9265,9 @@ static void Intel_Core_MicroArchitecture(CORE_RO *Core) 	/* Per P-Core */
 	    BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_AMP_Prefetch, Core->Bind);
 	}
 
-	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->PCORE_Mask, Core->Bind);
+	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->L2_AMP_Mask, Core->Bind);
+
+	Intel_Core_MicroArchControl(Core);
       }
 	break;
     case Hybrid_RSVD1:
@@ -9284,6 +9279,27 @@ static void Intel_Core_MicroArchitecture(CORE_RO *Core) 	/* Per P-Core */
   }
 }
 
+static void Intel_Ultra7_MicroArchitecture(CORE_RO *Core)
+{	/* 06_AA, 06_AB, 06_AC						*/
+	MISC_FEATURE_CONTROL MiscFeatCtrl = {.value = 0};
+	RDMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL);
+
+	switch (L1_NPP_PREFETCH_Disable) {
+	case COREFREQ_TOGGLE_OFF:
+	case COREFREQ_TOGGLE_ON:
+		MiscFeatCtrl.L1_NPP_Prefetch = L1_NPP_PREFETCH_Disable;
+		WRMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL);
+		RDMSR(MiscFeatCtrl, MSR_MISC_FEATURE_CONTROL);
+		break;
+	}
+	if (MiscFeatCtrl.L1_NPP_Prefetch == 1) {
+	    BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
+	} else {
+	    BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_NPP_Prefetch, Core->Bind);
+	}
+	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask, Core->Bind);
+}
+
 static void SpeedStep_Technology(CORE_RO *Core) 		/*Per Package*/
 {
   if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) {
@@ -12377,7 +12393,8 @@ static void PerCore_Reset(CORE_RO *Core)
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->TM_Mask	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->ODCM_Mask , Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->DCU_Mask  , Core->Bind);
-	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->PCORE_Mask, Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->L1_Scrub_Mask, Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->L2_AMP_Mask, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->ECORE_Mask, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->PowerMgmt_Mask, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RO(Proc))->SpeedStep_Mask, Core->Bind);
@@ -13468,7 +13485,7 @@ static void PerCore_Icelake_Query(void *arg)
 
 	PerCore_Skylake_Query(arg);
 
-	Intel_Core_MicroArchitecture(Core);
+	Intel_Core_MicroArchControl(Core);
 }
 
 static void PerCore_Tigerlake_Query(void *arg)
@@ -13477,7 +13494,35 @@ static void PerCore_Tigerlake_Query(void *arg)
 
 	PerCore_Kaby_Lake_Query(arg);
 
+	Intel_Core_MicroArchControl(Core);
+}
+
+static void PerCore_Alderlake_Query(void *arg)
+{
+	CORE_RO *Core = (CORE_RO *) arg;
+
+	PerCore_Kaby_Lake_Query(arg);
+
+	Intel_Core_MicroArchitecture(Core);
+}
+
+static void PerCore_Raptorlake_Query(void *arg)
+{
+	CORE_RO *Core = (CORE_RO *) arg;
+
+	PerCore_Skylake_Query(arg);
+
+	Intel_Core_MicroArchitecture(Core);
+}
+
+static void PerCore_Meteorlake_Query(void *arg)
+{
+	CORE_RO *Core = (CORE_RO *) arg;
+
+	PerCore_Kaby_Lake_Query(arg);
+
 	Intel_Core_MicroArchitecture(Core);
+	Intel_Ultra7_MicroArchitecture(Core);
 }
 
 static void PerCore_AMD_Family_0Fh_Query(void *arg)
diff --git a/x86_64/corefreqk.h b/x86_64/corefreqk.h
index bd5569d..2a2bbfb 100644
--- a/x86_64/corefreqk.h
+++ b/x86_64/corefreqk.h
@@ -1652,6 +1652,12 @@ static void PerCore_Icelake_Query(void *arg) ;
 
 static void PerCore_Tigerlake_Query(void *arg) ;
 
+static void PerCore_Alderlake_Query(void *arg) ;
+
+static void PerCore_Raptorlake_Query(void *arg) ;
+
+static void PerCore_Meteorlake_Query(void *arg) ;
+
 static void Query_AMD_Family_0Fh(unsigned int cpu) ;
 static void PerCore_AMD_Family_0Fh_Query(void *arg) ;
 static void Start_AMD_Family_0Fh(void *arg) ;
@@ -11076,7 +11082,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Alderlake_S] = {							/* 80*/
 	.Signature = _Alderlake_S,
 	.Query = Query_Skylake,
-	.Update = PerCore_Tigerlake_Query,
+	.Update = PerCore_Alderlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11100,7 +11106,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Alderlake_H] = {							/* 81*/
 	.Signature = _Alderlake_H,
 	.Query = Query_Skylake,
-	.Update = PerCore_Tigerlake_Query,
+	.Update = PerCore_Alderlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11149,7 +11155,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Meteorlake_M] = {							/* 83*/
 	.Signature = _Meteorlake_M,
 	.Query = Query_Skylake,
-	.Update = PerCore_Tigerlake_Query,
+	.Update = PerCore_Meteorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11173,7 +11179,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Meteorlake_N] = {							/* 84*/
 	.Signature = _Meteorlake_N,
 	.Query = Query_Skylake,
-	.Update = PerCore_Tigerlake_Query,
+	.Update = PerCore_Meteorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11197,7 +11203,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Meteorlake_S] = {							/* 85*/
 	.Signature = _Meteorlake_S,
 	.Query = Query_Skylake,
-	.Update = PerCore_Tigerlake_Query,
+	.Update = PerCore_Meteorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11222,7 +11228,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Raptorlake] = {							/* 86*/
 	.Signature = _Raptorlake,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11246,7 +11252,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Raptorlake_P] = {							/* 87*/
 	.Signature = _Raptorlake_P,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11270,7 +11276,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [Raptorlake_S] = {							/* 88*/
 	.Signature = _Raptorlake_S,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11294,7 +11300,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [LunarLake] = { 							/* 89*/
 	.Signature = _Lunarlake,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11318,7 +11324,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [ArrowLake] = { 							/* 90*/
 	.Signature = _Arrowlake,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11342,7 +11348,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [ArrowLake_H] = {							/* 91*/
 	.Signature = _Arrowlake_H,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11366,7 +11372,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [ArrowLake_U] = {							/* 92*/
 	.Signature = _Arrowlake_U,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,
@@ -11390,7 +11396,7 @@ static ARCH Arch[ARCHITECTURES] = {
 [PantherLake] = {							/* 93*/
 	.Signature = _Pantherlake,
 	.Query = Query_Skylake,
-	.Update = PerCore_Icelake_Query,
+	.Update = PerCore_Raptorlake_Query,
 	.Start = Start_Alderlake,
 	.Stop = Stop_Alderlake,
 	.Exit = NULL,