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CoreFreq
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Mirror of https://github.com/cyring/CoreFreq
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develop
[Intel] Added method `CLOCK_FLEX_MAX` with Xeon's Nehalem & Core 2
CyrIng
37 hours
master
[CLI] Make HDCP meaning string shorter
CyrIng
4 days
Tag
Download
Author
Age
1.97.2
commit 6caa79d69c...
CyrIng
3 weeks
1.97.2-x86_64
commit 29c8c1f8f4...
CyrIng
5 weeks
1.97.1
commit 3a25d36977...
CyrIng
9 weeks
1.97.0
commit 93db56941e...
CyrIng
5 months
1.96.5
commit 150a2191f3...
CyrIng
11 months
1.96.4
commit 49fce8116b...
CyrIng
12 months
1.96.3
commit 706460f852...
CyrIng
12 months
1.96.2
commit bdd9400a86...
CyrIng
12 months
1.96.1
commit a28ea7bea3...
CyrIng
13 months
1.96.0
commit 11bdf0a545...
CyrIng
13 months
[...]
Age
Commit message
Author
2024-04-05
Version 1.97.1
1.97.1
CyrIng
2024-04-05
[AMD][Ryzen] Adding the Embedded 7000 and 8000 Series
CyrIng
2024-04-05
[AMD] CPUID bits completeness
CyrIng
2024-04-03
[AMD][Ryzen] Adding other Rembrandt-R and Dragon Range processors
CyrIng
2024-03-30
[Intel] Added the ArrowLake/U entry
CyrIng
2024-03-30
[CLI] Fix spacing within the Power Monitor print
CyrIng
2024-03-30
[CR] Check source code width
CyrIng
2024-03-25
[AMD][Zen] Don't process APU' topology as CPU Complex
CyrIng
2024-03-24
[AArch64] When big.LITTLE detected, classify CPUs in Pcore & Ecore
CyrIng
2024-03-24
[AArch64] Estimates C1 counter from normalized TSC
CyrIng
[...]
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