index
:
CoreFreq
develop
master
Mirror of https://github.com/cyring/CoreFreq
matthias
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Branch
Commit message
Author
Age
develop
[Intel] Added method `CLOCK_FLEX_MAX` with Xeon's Nehalem & Core 2
CyrIng
37 hours
master
[CLI] Make HDCP meaning string shorter
CyrIng
4 days
Tag
Download
Author
Age
1.97.2
commit 6caa79d69c...
CyrIng
3 weeks
1.97.2-x86_64
commit 29c8c1f8f4...
CyrIng
5 weeks
1.97.1
commit 3a25d36977...
CyrIng
9 weeks
1.97.0
commit 93db56941e...
CyrIng
5 months
1.96.5
commit 150a2191f3...
CyrIng
11 months
1.96.4
commit 49fce8116b...
CyrIng
12 months
1.96.3
commit 706460f852...
CyrIng
12 months
1.96.2
commit bdd9400a86...
CyrIng
12 months
1.96.1
commit a28ea7bea3...
CyrIng
13 months
1.96.0
commit 11bdf0a545...
CyrIng
13 months
[...]
Age
Commit message
Author
2023-05-13
[AMD] Adding EPYC Embedded 7001 Series as Naples
1.96.1
CyrIng
2023-05-13
[AMD] Adding EPYC Embedded 7002 Series as Rome
CyrIng
2023-05-13
[AMD] Adding EPYC Embedded 7003 Series as Milan
CyrIng
2023-05-13
[AMD] Adding EPYC Embedded 9004 Series as Genoa
CyrIng
2023-05-13
AMD Ryzen Z1 CPUID' brand fix
CyrIng
2023-05-13
[Idle] Clear interrupt flag after Halt
CyrIng
2023-05-08
[KERNEL] Change `class_create()` according to Linux 6.4
CyrIng
2023-05-06
Postpone ClockSource registration at startup until BaseClock is computed.
CyrIng
2023-05-02
[AMD][PHOENIX] Adding Ryzen 7940H, 7840H, 7640H
CyrIng
2023-04-27
[AMD][RPL/X3D] Disabling the turbo boosted P-states change
1.96.0
CyrIng
[...]
Clone
http://git.beyermatthi.as/CoreFreq
https://git.beyermatthi.as/CoreFreq
git://git.beyermatthi.as/CoreFreq
git@git.beyermatthi.as:CoreFreq