CoreFreq - Mirror of https://github.com/cyring/CoreFreq

Branch	Commit message	Author	Age
develop	[CR] Prevent array size overflow	CyrIng	3 days
master	[Doc] `CONFIG_TRIM_UNUSED_KSYMS` kernel build config is forbidden	CyrIng	14 days

Tag	Download	Author	Age
1.97.2	commit 6caa79d69c...	CyrIng	14 days
1.97.2-x86_64	commit 29c8c1f8f4...	CyrIng	4 weeks
1.97.1	commit 3a25d36977...	CyrIng	8 weeks
1.97.0	commit 93db56941e...	CyrIng	4 months
1.96.5	commit 150a2191f3...	CyrIng	11 months
1.96.4	commit 49fce8116b...	CyrIng	12 months
1.96.3	commit 706460f852...	CyrIng	12 months
1.96.2	commit bdd9400a86...	CyrIng	12 months
1.96.1	commit a28ea7bea3...	CyrIng	13 months
1.96.0	commit 11bdf0a545...	CyrIng	13 months
[...]

Age	Commit message	Author
2023-02-18	[Intel 11th to 14th gen] Convert DRAM Speed to MT/s1.95.4	CyrIng
2023-02-18	[Intel 11th to 14th gen] Compute Bus Rate based on BIOS MC PLL	CyrIng
2023-02-17	[Intel][Airmont] Fixed the Bus and DRAM frequency rates (#399)1.95.3	CyrIng
2023-02-14	[Intel 11th to 14th gen] Monitor SA voltage when ARCH_PMC=PCU built	CyrIng
2023-02-14	[Intel][Core i7-12700H] Attempt to decode TCO Watchdog	CyrIng
2023-02-14	[Intel:up to 13th gen] Attempt to probe the interleaved controllers	CyrIng
2023-02-12	[Intel] Introducing Spreadtrum as an Airmont architecture	CyrIng
2023-02-09	[Intel] Improving the Airmont IMC geometry	CyrIng
2023-02-05	[Intel][Airmont][Silvermont] Attempt to decode `tCKE` from DRMC1.95.2	CyrIng
2023-02-05	[Intel][Airmont] Adding a new IMC decoder (DRAM timings)	CyrIng
[...]

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