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path: root/drivers/clk/tegra/clk.h
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2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko
CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko
There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko
CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo
The EMC clock needs to carefully coordinate with the EMC controller programming to make sure external memory can be properly clocked. Do so by hooking up the EMC clock with an EMC provider that will specify which rates are supported by the EMC and provide a callback to use for setting the clock rate at the EMC. Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding
This code is only used on Tegra124, so rename it accordingly to make it more consistent with other file names. While at it, also get rid of the TEGRA_CLK_EMC Kconfig symbol that's really just an alias for TEGRA124_EMC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni
All the CAR controller settings are lost on suspend when core power goes off. This implement saving and restoring context for all PLLs and clocks during system suspend and resume to have the clocks back to same state for normal operation. Clock driver suspend and resume are registered as syscore_ops as clocks restore need to happen before the other drivers resume to have all their clocks back to the same state as before suspend. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni
Move CLK_OUT_ENB and RST_DEVICES registers to clk.h to share these with Tegra clock driver. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni
This patch has a fix to enable PLLP branches to CPU before changing the CPU cluster clock source to PLLP for Gen5 Super clock and disables PLLP branches to CPU when not in use. During system suspend entry and exit, CPU source will be switched to PLLP and this needs PLLP branches to be enabled to CPU prior to the switch. On system resume, warmboot code enables PLLP branches to CPU and powers up the CPU with PLLP clock source. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni
This patch adds support for saving OSC clock frequency and the drive-strength during OSC clock init and creates an API to restore OSC control register value from the saved context. This API is invoked by Tegra210 clock driver during system resume to restore the OSC clock settings. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up. The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter
The maximum frequency supported for I2S on Tegra124 and Tegra210 is 24.576MHz (as stated in the Tegra TK1 data sheet for Tegra124 and the Jetson TX1 module data sheet for Tegra210). However, the maximum I2S frequency is limited to 24MHz because that is the maximum frequency of the audio sync clock. Increase the maximum audio sync clock frequency to 24.576MHz for Tegra124 and Tegra210 in order to support 24.576MHz for I2S. Update the tegra_clk_register_sync_source() function so that it does not set the initial rate for the sync clocks and use the clock init tables to set the initial rate instead. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo
Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user may expect parent clock to be enabled by the child, so let's return -EPROBE_DEFER till parent clock appears. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver
To ensure writes to clock registers have properly propagated through the clock control logic and state machines, we need to ensure the writes have been posted in the registers and wait for 1us after that. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-19clk: tegra: Add peripheral clock registration helperThierry Reding
There is a common pattern that registers individual peripheral clocks from an initialization table. Add a common implementation to remove the duplication from various call sites. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-23clk: tegra: Re-factor T210 PLLX registrationAlex Frid
Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-20clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding
The recent conversion of proper const usage was only partial and didn't include Tegra20 and Tegra30 support. Fix that up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver
Add a super clock type which implements both mux and divider. This is used for aclk. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver
checkpatch now warns for const ** and expects const * const * to be used instead. This means we have to update the prototypes and function declarations to handle this change. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver
When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker
Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: define PLLRE_OUT1 register offset] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding
The peripheral clock registers are defined in static tables. These tables never need to be modified at runtime, so they can reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein
Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang
Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add logic for SSBill Huang
Add some logic for Spread Spectrum control. It is used in conjuncture with SDM fractional dividers. SSC has to be disabled when we configure the divider settings. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein
Add a callback to the pll_params for custom dynamic ramping functions which can be specified per PLL. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang
Add logic which (if specified for a pll) can verify that a PLL is set to the proper default value and if not can set it. This can be specified per PLL as each will have different default values. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang
This code makes use of the SDM fractional divider if present to constrain the allowable programming range of the PLL divider register bitfields to take advantage of higher frequency granularity that can be induced by the SDM divider. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register and handle PLLMB. PLLMB is used to allow switching between 2 PLLM's without having to use and intermediate backup PLL, as we need to lock the PLL before we can switch to it. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein
On Tegra210 SoC's, the logic to enable several of the plls is different from previous generations. Therefore, add registration functions specific to Tegra210 which will handle them appropriately. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang
If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein
For Tegra210, the logic to calculate out-of-table rates is different from previous generations. Add callbacks that can be overridden to allow for different ways of calculating rates. Default to _cal_rate when not specified. This patch also includes a new flag which is used to set which method of fixed_mdiv calculation is used. The new method for calculating the fixed divider value for M can be more accurate especially when fractional dividers are in play. This allows for older chipsets to use the existing logic and new generations to use a newer version which may work better for them. Based on original work by Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into the equation to calculate the effective N value for PLL which supports fractional divider. The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer feedback divider. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang
New SoC's may have more than 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein
Create a wrapper interface to make use of the existing clk_pll_wait_for_lock. This will be useful for implementations of callbacks in Tegra SoC specific clock drivers. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding
This is static data that is never modified, so make it const. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein
tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-20clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding
Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by: Benson Leung <bleung@chromium.org> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-20clk: tegra: Fix comments for structure definitionsRhyland Klein
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params struct. Update the struct comments to reflect where the fields really are. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen
This patch allows SoC-specific CAR initialization routines to register their own reset_assert and reset_deassert callbacks with the common Tegra CAR code. If defined, the common code will call these callbacks when a reset control with number >= num_periph_banks * 32 is attempted to be asserted or deasserted respectively. Numbers greater than or equal to num_periph_banks * 32 are used to avoid clashes with low numbers that are automatically mapped to standard CAR reset lines. Each SoC with these special resets should specify the defined reset control numbers in a device tree header file. Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-13clk: tegra: EMC clock driver depends on EMC driverThierry Reding
The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-13clk: tegra: Add EMC clock driverMikko Perttunen
The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10clk: tegra: Model oscillator as clockThierry Reding
Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-10clk: tegra: Fix typo tabel -> tableThierry Reding
The clock initialization structure is named struct clk_init_table. Update the kerneldoc comment to use the correct name. Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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