diff options
| author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 17:28:26 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 18:05:04 +0100 |
| commit | fde207eb15115f1081e589267ebdf442aa54cda5 (patch) | |
| tree | d6f9907076138f33db9691e28d8b6bcfded1a214 /drivers/clk/tegra/clk.h | |
| parent | 407254da291c03c32109881ca8cbda5607714a8f (diff) | |
clk: tegra: pll: Add code to handle if resets are supported by PLL
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ae09a3139df2..adf2e8ead335 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -176,6 +176,8 @@ struct div_nmp { * @lock_enable_bit_idx: Bit index to enable PLL lock * @iddq_reg: PLL IDDQ register offset * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @reset_reg: Register offset of where RESET bit is + * @reset_bit_idx: Shift of reset bit in reset_reg * @sdm_din_reg: Register offset where SDM settings are * @sdm_din_mask: Mask of SDM divider bits * @sdm_ctrl_reg: Register offset where SDM enable is @@ -239,6 +241,8 @@ struct tegra_clk_pll_params { u32 lock_enable_bit_idx; u32 iddq_reg; u32 iddq_bit_idx; + u32 reset_reg; + u32 reset_bit_idx; u32 sdm_din_reg; u32 sdm_din_mask; u32 sdm_ctrl_reg; |