diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/hisilicon')
4 files changed, 142 insertions, 51 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json index 9f0f15d15f75..a4a6408639b4 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json @@ -1,122 +1,122 @@ [ { - "ArchStdEvent": "L1D_CACHE_RD", + "ArchStdEvent": "L1D_CACHE_RD" }, { - "ArchStdEvent": "L1D_CACHE_WR", + "ArchStdEvent": "L1D_CACHE_WR" }, { - "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "ArchStdEvent": "L1D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L1D_CACHE_REFILL_WR", + "ArchStdEvent": "L1D_CACHE_REFILL_WR" }, { - "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" }, { - "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" }, { - "ArchStdEvent": "L1D_CACHE_INVAL", + "ArchStdEvent": "L1D_CACHE_INVAL" }, { - "ArchStdEvent": "L1D_TLB_REFILL_RD", + "ArchStdEvent": "L1D_TLB_REFILL_RD" }, { - "ArchStdEvent": "L1D_TLB_REFILL_WR", + "ArchStdEvent": "L1D_TLB_REFILL_WR" }, { - "ArchStdEvent": "L1D_TLB_RD", + "ArchStdEvent": "L1D_TLB_RD" }, { - "ArchStdEvent": "L1D_TLB_WR", + "ArchStdEvent": "L1D_TLB_WR" }, { - "ArchStdEvent": "L2D_CACHE_RD", + "ArchStdEvent": "L2D_CACHE_RD" }, { - "ArchStdEvent": "L2D_CACHE_WR", + "ArchStdEvent": "L2D_CACHE_WR" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "ArchStdEvent": "L2D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "ArchStdEvent": "L2D_CACHE_REFILL_WR" }, { - "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" }, { - "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" }, { - "ArchStdEvent": "L2D_CACHE_INVAL", + "ArchStdEvent": "L2D_CACHE_INVAL" }, { "PublicDescription": "Level 1 instruction cache prefetch access count", "EventCode": "0x102e", "EventName": "L1I_CACHE_PRF", - "BriefDescription": "L1I cache prefetch access count", + "BriefDescription": "L1I cache prefetch access count" }, { "PublicDescription": "Level 1 instruction cache miss due to prefetch access count", "EventCode": "0x102f", "EventName": "L1I_CACHE_PRF_REFILL", - "BriefDescription": "L1I cache miss due to prefetch access count", + "BriefDescription": "L1I cache miss due to prefetch access count" }, { "PublicDescription": "Instruction queue is empty", "EventCode": "0x1043", "EventName": "IQ_IS_EMPTY", - "BriefDescription": "Instruction queue is empty", + "BriefDescription": "Instruction queue is empty" }, { "PublicDescription": "Instruction fetch stall cycles", "EventCode": "0x1044", "EventName": "IF_IS_STALL", - "BriefDescription": "Instruction fetch stall cycles", + "BriefDescription": "Instruction fetch stall cycles" }, { "PublicDescription": "Instructions can receive, but not send", "EventCode": "0x2014", "EventName": "FETCH_BUBBLE", - "BriefDescription": "Instructions can receive, but not send", + "BriefDescription": "Instructions can receive, but not send" }, { "PublicDescription": "Prefetch request from LSU", "EventCode": "0x6013", "EventName": "PRF_REQ", - "BriefDescription": "Prefetch request from LSU", + "BriefDescription": "Prefetch request from LSU" }, { "PublicDescription": "Hit on prefetched data", "EventCode": "0x6014", "EventName": "HIT_ON_PRF", - "BriefDescription": "Hit on prefetched data", + "BriefDescription": "Hit on prefetched data" }, { "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4", "EventCode": "0x7001", "EventName": "EXE_STALL_CYCLE", - "BriefDescription": "Cycles of that the number of issue ups are less than 4", + "BriefDescription": "Cycles of that the number of issue ups are less than 4" }, { "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", "EventCode": "0x7004", "EventName": "MEM_STALL_ANYLOAD", - "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved" }, { "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", "EventCode": "0x7006", "EventName": "MEM_STALL_L1MISS", - "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill" }, { "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", "EventCode": "0x7007", "EventName": "MEM_STALL_L2MISS", - "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache", - }, + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache" + } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json index 0d1556fcdffe..61514d38601b 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json @@ -1,44 +1,58 @@ [ { + "EventCode": "0x00", + "EventName": "uncore_hisi_ddrc.flux_wr", + "BriefDescription": "DDRC total write operations", + "PublicDescription": "DDRC total write operations", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x01", + "EventName": "uncore_hisi_ddrc.flux_rd", + "BriefDescription": "DDRC total read operations", + "PublicDescription": "DDRC total read operations", + "Unit": "hisi_sccl,ddrc" + }, + { "EventCode": "0x02", "EventName": "uncore_hisi_ddrc.flux_wcmd", "BriefDescription": "DDRC write commands", "PublicDescription": "DDRC write commands", - "Unit": "hisi_sccl,ddrc", + "Unit": "hisi_sccl,ddrc" }, { "EventCode": "0x03", "EventName": "uncore_hisi_ddrc.flux_rcmd", "BriefDescription": "DDRC read commands", "PublicDescription": "DDRC read commands", - "Unit": "hisi_sccl,ddrc", + "Unit": "hisi_sccl,ddrc" }, { "EventCode": "0x04", - "EventName": "uncore_hisi_ddrc.flux_wr", + "EventName": "uncore_hisi_ddrc.pre_cmd", "BriefDescription": "DDRC precharge commands", "PublicDescription": "DDRC precharge commands", - "Unit": "hisi_sccl,ddrc", + "Unit": "hisi_sccl,ddrc" }, { "EventCode": "0x05", "EventName": "uncore_hisi_ddrc.act_cmd", "BriefDescription": "DDRC active commands", "PublicDescription": "DDRC active commands", - "Unit": "hisi_sccl,ddrc", + "Unit": "hisi_sccl,ddrc" }, { "EventCode": "0x06", "EventName": "uncore_hisi_ddrc.rnk_chg", "BriefDescription": "DDRC rank commands", "PublicDescription": "DDRC rank commands", - "Unit": "hisi_sccl,ddrc", + "Unit": "hisi_sccl,ddrc" }, { "EventCode": "0x07", "EventName": "uncore_hisi_ddrc.rw_chg", "BriefDescription": "DDRC read and write changes", "PublicDescription": "DDRC read and write changes", - "Unit": "hisi_sccl,ddrc", - }, + "Unit": "hisi_sccl,ddrc" + } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json index 447d3064de90..ada86782933f 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json @@ -4,48 +4,69 @@ "EventName": "uncore_hisi_hha.rx_ops_num", "BriefDescription": "The number of all operations received by the HHA", "PublicDescription": "The number of all operations received by the HHA", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x01", "EventName": "uncore_hisi_hha.rx_outer", "BriefDescription": "The number of all operations received by the HHA from another socket", "PublicDescription": "The number of all operations received by the HHA from another socket", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x02", "EventName": "uncore_hisi_hha.rx_sccl", "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket", "PublicDescription": "The number of all operations received by the HHA from another SCCL in this socket", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x03", + "EventName": "uncore_hisi_hha.rx_ccix", + "BriefDescription": "Count of the number of operations that HHA has received from CCIX", + "PublicDescription": "Count of the number of operations that HHA has received from CCIX", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x1c", "EventName": "uncore_hisi_hha.rd_ddr_64b", "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes", "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x1d", - "EventName": "uncore_hisi_hha.wr_dr_64b", + "EventName": "uncore_hisi_hha.wr_ddr_64b", "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes", "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x1e", "EventName": "uncore_hisi_hha.rd_ddr_128b", "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes", "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, { "EventCode": "0x1f", "EventName": "uncore_hisi_hha.wr_ddr_128b", "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes", "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes", - "Unit": "hisi_sccl,hha", + "Unit": "hisi_sccl,hha" }, + { + "EventCode": "0x20", + "EventName": "uncore_hisi_hha.spill_num", + "BriefDescription": "Count of the number of spill operations that the HHA has sent", + "PublicDescription": "Count of the number of spill operations that the HHA has sent", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x21", + "EventName": "uncore_hisi_hha.spill_success", + "BriefDescription": "Count of the number of successful spill operations that the HHA has sent", + "PublicDescription": "Count of the number of successful spill operations that the HHA has sent", + "Unit": "hisi_sccl,hha" + } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json index ca48747642e1..67ab19e8cf3a 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json @@ -4,34 +4,90 @@ "EventName": "uncore_hisi_l3c.rd_cpipe", "BriefDescription": "Total read accesses", "PublicDescription": "Total read accesses", - "Unit": "hisi_sccl,l3c", + "Unit": "hisi_sccl,l3c" }, { "EventCode": "0x01", "EventName": "uncore_hisi_l3c.wr_cpipe", "BriefDescription": "Total write accesses", "PublicDescription": "Total write accesses", - "Unit": "hisi_sccl,l3c", + "Unit": "hisi_sccl,l3c" }, { "EventCode": "0x02", "EventName": "uncore_hisi_l3c.rd_hit_cpipe", "BriefDescription": "Total read hits", "PublicDescription": "Total read hits", - "Unit": "hisi_sccl,l3c", + "Unit": "hisi_sccl,l3c" }, { "EventCode": "0x03", "EventName": "uncore_hisi_l3c.wr_hit_cpipe", "BriefDescription": "Total write hits", "PublicDescription": "Total write hits", - "Unit": "hisi_sccl,l3c", + "Unit": "hisi_sccl,l3c" }, { "EventCode": "0x04", "EventName": "uncore_hisi_l3c.victim_num", "BriefDescription": "l3c precharge commands", "PublicDescription": "l3c precharge commands", - "Unit": "hisi_sccl,l3c", + "Unit": "hisi_sccl,l3c" }, + { + "EventCode": "0x20", + "EventName": "uncore_hisi_l3c.rd_spipe", + "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe", + "PublicDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x21", + "EventName": "uncore_hisi_l3c.wr_spipe", + "BriefDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe", + "PublicDescription": "Count of the number of write lines that come from this cluster of CPU core in spipe", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x22", + "EventName": "uncore_hisi_l3c.rd_hit_spipe", + "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C", + "PublicDescription": "Count of the number of read lines that hits in spipe of this L3C", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x23", + "EventName": "uncore_hisi_l3c.wr_hit_spipe", + "BriefDescription": "Count of the number of write lines that hits in spipe of this L3C", + "PublicDescription": "Count of the number of write lines that hits in spipe of this L3C", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x29", + "EventName": "uncore_hisi_l3c.back_invalid", + "BriefDescription": "Count of the number of L3C back invalid operations", + "PublicDescription": "Count of the number of L3C back invalid operations", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x40", + "EventName": "uncore_hisi_l3c.retry_cpu", + "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations", + "PublicDescription": "Count of the number of retry that L3C suppresses the CPU operations", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x41", + "EventName": "uncore_hisi_l3c.retry_ring", + "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations", + "PublicDescription": "Count of the number of retry that L3C suppresses the ring operations", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x42", + "EventName": "uncore_hisi_l3c.prefetch_drop", + "BriefDescription": "Count of the number of prefetch drops from this L3C", + "PublicDescription": "Count of the number of prefetch drops from this L3C", + "Unit": "hisi_sccl,l3c" + } ] |