diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64')
19 files changed, 388 insertions, 297 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json index abc98b018446..2d15b11e5383 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json @@ -1,12 +1,12 @@ [ { - "ArchStdEvent": "BR_IMMED_SPEC", + "ArchStdEvent": "BR_IMMED_SPEC" }, { - "ArchStdEvent": "BR_RETURN_SPEC", + "ArchStdEvent": "BR_RETURN_SPEC" }, { - "ArchStdEvent": "BR_INDIRECT_SPEC", + "ArchStdEvent": "BR_INDIRECT_SPEC" }, { "PublicDescription": "Mispredicted or not predicted branch speculatively executed", @@ -19,5 +19,5 @@ "EventCode": "0x12", "EventName": "BR_PRED", "BriefDescription": "Predictable branch" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json index 687b2629e1d1..5c1a9a922ca4 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json @@ -1,26 +1,26 @@ [ { - "ArchStdEvent": "BUS_ACCESS_RD", + "ArchStdEvent": "BUS_ACCESS_RD" }, { - "ArchStdEvent": "BUS_ACCESS_WR", + "ArchStdEvent": "BUS_ACCESS_WR" }, { - "ArchStdEvent": "BUS_ACCESS_SHARED", + "ArchStdEvent": "BUS_ACCESS_SHARED" }, { - "ArchStdEvent": "BUS_ACCESS_NOT_SHARED", + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" }, { - "ArchStdEvent": "BUS_ACCESS_NORMAL", + "ArchStdEvent": "BUS_ACCESS_NORMAL" }, { - "ArchStdEvent": "BUS_ACCESS_PERIPH", + "ArchStdEvent": "BUS_ACCESS_PERIPH" }, { "PublicDescription": "Bus access", "EventCode": "0x19", "EventName": "BUS_ACCESS", "BriefDescription": "Bus access" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json index df9201434cb6..40010a8724b3 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json @@ -1,42 +1,42 @@ [ { - "ArchStdEvent": "L1D_CACHE_RD", + "ArchStdEvent": "L1D_CACHE_RD" }, { - "ArchStdEvent": "L1D_CACHE_WR", + "ArchStdEvent": "L1D_CACHE_WR" }, { - "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "ArchStdEvent": "L1D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L1D_CACHE_INVAL", + "ArchStdEvent": "L1D_CACHE_INVAL" }, { - "ArchStdEvent": "L1D_TLB_REFILL_RD", + "ArchStdEvent": "L1D_TLB_REFILL_RD" }, { - "ArchStdEvent": "L1D_TLB_REFILL_WR", + "ArchStdEvent": "L1D_TLB_REFILL_WR" }, { - "ArchStdEvent": "L2D_CACHE_RD", + "ArchStdEvent": "L2D_CACHE_RD" }, { - "ArchStdEvent": "L2D_CACHE_WR", + "ArchStdEvent": "L2D_CACHE_WR" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "ArchStdEvent": "L2D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "ArchStdEvent": "L2D_CACHE_REFILL_WR" }, { - "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" }, { - "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" }, { - "ArchStdEvent": "L2D_CACHE_INVAL", + "ArchStdEvent": "L2D_CACHE_INVAL" }, { "PublicDescription": "Level 1 instruction cache refill", @@ -187,5 +187,5 @@ "EventCode": "0x116", "EventName": "PAGE_WALK_L2_STAGE2_HIT", "BriefDescription": "Page walk, L2 stage-2 hit" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json index 38cd1f1a70dc..51d1dc1519b2 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json @@ -16,5 +16,5 @@ "EventCode": "0x110", "EventName": "Wait_CYCLES", "BriefDescription": "Wait state cycle" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json index 3720dc28a15f..66e51bc64b22 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json @@ -1,39 +1,39 @@ [ { - "ArchStdEvent": "EXC_UNDEF", + "ArchStdEvent": "EXC_UNDEF" }, { - "ArchStdEvent": "EXC_SVC", + "ArchStdEvent": "EXC_SVC" }, { - "ArchStdEvent": "EXC_PABORT", + "ArchStdEvent": "EXC_PABORT" }, { - "ArchStdEvent": "EXC_DABORT", + "ArchStdEvent": "EXC_DABORT" }, { - "ArchStdEvent": "EXC_IRQ", + "ArchStdEvent": "EXC_IRQ" }, { - "ArchStdEvent": "EXC_FIQ", + "ArchStdEvent": "EXC_FIQ" }, { - "ArchStdEvent": "EXC_HVC", + "ArchStdEvent": "EXC_HVC" }, { - "ArchStdEvent": "EXC_TRAP_PABORT", + "ArchStdEvent": "EXC_TRAP_PABORT" }, { - "ArchStdEvent": "EXC_TRAP_DABORT", + "ArchStdEvent": "EXC_TRAP_DABORT" }, { - "ArchStdEvent": "EXC_TRAP_OTHER", + "ArchStdEvent": "EXC_TRAP_OTHER" }, { - "ArchStdEvent": "EXC_TRAP_IRQ", + "ArchStdEvent": "EXC_TRAP_IRQ" }, { - "ArchStdEvent": "EXC_TRAP_FIQ", + "ArchStdEvent": "EXC_TRAP_FIQ" }, { "PublicDescription": "Exception taken", @@ -46,5 +46,5 @@ "EventCode": "0x0a", "EventName": "EXC_RETURN", "BriefDescription": "Exception return" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json index 82cf753e6472..0d3e46776642 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json @@ -1,42 +1,42 @@ [ { - "ArchStdEvent": "LD_SPEC", + "ArchStdEvent": "LD_SPEC" }, { - "ArchStdEvent": "ST_SPEC", + "ArchStdEvent": "ST_SPEC" }, { - "ArchStdEvent": "LDST_SPEC", + "ArchStdEvent": "LDST_SPEC" }, { - "ArchStdEvent": "DP_SPEC", + "ArchStdEvent": "DP_SPEC" }, { - "ArchStdEvent": "ASE_SPEC", + "ArchStdEvent": "ASE_SPEC" }, { - "ArchStdEvent": "VFP_SPEC", + "ArchStdEvent": "VFP_SPEC" }, { - "ArchStdEvent": "PC_WRITE_SPEC", + "ArchStdEvent": "PC_WRITE_SPEC" }, { - "ArchStdEvent": "CRYPTO_SPEC", + "ArchStdEvent": "CRYPTO_SPEC" }, { - "ArchStdEvent": "ISB_SPEC", + "ArchStdEvent": "ISB_SPEC" }, { - "ArchStdEvent": "DSB_SPEC", + "ArchStdEvent": "DSB_SPEC" }, { - "ArchStdEvent": "DMB_SPEC", + "ArchStdEvent": "DMB_SPEC" }, { - "ArchStdEvent": "RC_LD_SPEC", + "ArchStdEvent": "RC_LD_SPEC" }, { - "ArchStdEvent": "RC_ST_SPEC", + "ArchStdEvent": "RC_ST_SPEC" }, { "PublicDescription": "Instruction architecturally executed, software increment", @@ -85,5 +85,5 @@ "EventCode": "0x100", "EventName": "NOP_SPEC", "BriefDescription": "Speculatively executed, NOP" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json index 2aecc5c2347d..7ecffb989ae0 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json @@ -1,14 +1,14 @@ [ { - "ArchStdEvent": "LDREX_SPEC", + "ArchStdEvent": "LDREX_SPEC" }, { - "ArchStdEvent": "STREX_PASS_SPEC", + "ArchStdEvent": "STREX_PASS_SPEC" }, { - "ArchStdEvent": "STREX_FAIL_SPEC", + "ArchStdEvent": "STREX_FAIL_SPEC" }, { - "ArchStdEvent": "STREX_SPEC", - }, + "ArchStdEvent": "STREX_SPEC" + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json index 08508697b318..c2fe674df960 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json @@ -1,18 +1,18 @@ [ { - "ArchStdEvent": "MEM_ACCESS_RD", + "ArchStdEvent": "MEM_ACCESS_RD" }, { - "ArchStdEvent": "MEM_ACCESS_WR", + "ArchStdEvent": "MEM_ACCESS_WR" }, { - "ArchStdEvent": "UNALIGNED_LD_SPEC", + "ArchStdEvent": "UNALIGNED_LD_SPEC" }, { - "ArchStdEvent": "UNALIGNED_ST_SPEC", + "ArchStdEvent": "UNALIGNED_ST_SPEC" }, { - "ArchStdEvent": "UNALIGNED_LDST_SPEC", + "ArchStdEvent": "UNALIGNED_LDST_SPEC" }, { "PublicDescription": "Data memory access", @@ -25,5 +25,5 @@ "EventCode": "0x1a", "EventName": "MEM_ERROR", "BriefDescription": "Memory error" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json index e2087de586bf..17c71aba6612 100644 --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json @@ -46,5 +46,5 @@ "EventCode": "0x10f", "EventName": "FX_STALL", "BriefDescription": "FX stalled" - }, + } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json index 0b0e6b26605b..8f5cf88aaf38 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json @@ -1,6 +1,6 @@ [ { - "ArchStdEvent": "BR_INDIRECT_SPEC", + "ArchStdEvent": "BR_INDIRECT_SPEC" }, { "EventCode": "0xC9", diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json index ce33b2553277..0a70b82f753f 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json @@ -1,8 +1,8 @@ [ { - "ArchStdEvent": "BUS_ACCESS_RD", + "ArchStdEvent": "BUS_ACCESS_RD" }, { - "ArchStdEvent": "BUS_ACCESS_WR", + "ArchStdEvent": "BUS_ACCESS_WR" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json index 6cc6cbd7bf0b..e9f7e4c3900d 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json @@ -1,9 +1,9 @@ [ { - "ArchStdEvent": "EXC_IRQ", + "ArchStdEvent": "EXC_IRQ" }, { - "ArchStdEvent": "EXC_FIQ", + "ArchStdEvent": "EXC_FIQ" }, { "EventCode": "0xC6", diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json index 0ac9b7927450..543c7692677a 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json @@ -1,179 +1,179 @@ [ { - "ArchStdEvent": "L1D_CACHE_RD", + "ArchStdEvent": "L1D_CACHE_RD" }, { - "ArchStdEvent": "L1D_CACHE_WR", + "ArchStdEvent": "L1D_CACHE_WR" }, { - "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "ArchStdEvent": "L1D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L1D_CACHE_REFILL_WR", + "ArchStdEvent": "L1D_CACHE_REFILL_WR" }, { - "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" }, { - "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" }, { - "ArchStdEvent": "L1D_CACHE_INVAL", + "ArchStdEvent": "L1D_CACHE_INVAL" }, { - "ArchStdEvent": "L1D_TLB_REFILL_RD", + "ArchStdEvent": "L1D_TLB_REFILL_RD" }, { - "ArchStdEvent": "L1D_TLB_REFILL_WR", + "ArchStdEvent": "L1D_TLB_REFILL_WR" }, { - "ArchStdEvent": "L2D_CACHE_RD", + "ArchStdEvent": "L2D_CACHE_RD" }, { - "ArchStdEvent": "L2D_CACHE_WR", + "ArchStdEvent": "L2D_CACHE_WR" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "ArchStdEvent": "L2D_CACHE_REFILL_RD" }, { - "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "ArchStdEvent": "L2D_CACHE_REFILL_WR" }, { - "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" }, { - "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" }, { - "ArchStdEvent": "L2D_CACHE_INVAL", + "ArchStdEvent": "L2D_CACHE_INVAL" }, { - "ArchStdEvent": "BUS_ACCESS_RD", + "ArchStdEvent": "BUS_ACCESS_RD" }, { - "ArchStdEvent": "BUS_ACCESS_WR", + "ArchStdEvent": "BUS_ACCESS_WR" }, { - "ArchStdEvent": "BUS_ACCESS_SHARED", + "ArchStdEvent": "BUS_ACCESS_SHARED" }, { - "ArchStdEvent": "BUS_ACCESS_NOT_SHARED", + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" }, { - "ArchStdEvent": "BUS_ACCESS_NORMAL", + "ArchStdEvent": "BUS_ACCESS_NORMAL" }, { - "ArchStdEvent": "BUS_ACCESS_PERIPH", + "ArchStdEvent": "BUS_ACCESS_PERIPH" }, { - "ArchStdEvent": "MEM_ACCESS_RD", + "ArchStdEvent": "MEM_ACCESS_RD" }, { - "ArchStdEvent": "MEM_ACCESS_WR", + "ArchStdEvent": "MEM_ACCESS_WR" }, { - "ArchStdEvent": "UNALIGNED_LD_SPEC", + "ArchStdEvent": "UNALIGNED_LD_SPEC" }, { - "ArchStdEvent": "UNALIGNED_ST_SPEC", + "ArchStdEvent": "UNALIGNED_ST_SPEC" }, { - "ArchStdEvent": "UNALIGNED_LDST_SPEC", + "ArchStdEvent": "UNALIGNED_LDST_SPEC" }, { - "ArchStdEvent": "LDREX_SPEC", + "ArchStdEvent": "LDREX_SPEC" }, { - "ArchStdEvent": "STREX_PASS_SPEC", + "ArchStdEvent": "STREX_PASS_SPEC" }, { - "ArchStdEvent": "STREX_FAIL_SPEC", + "ArchStdEvent": "STREX_FAIL_SPEC" }, { - "ArchStdEvent": "LD_SPEC", + "ArchStdEvent": "LD_SPEC" }, { - "ArchStdEvent": "ST_SPEC", + "ArchStdEvent": "ST_SPEC" }, { - "ArchStdEvent": "LDST_SPEC", + "ArchStdEvent": "LDST_SPEC" }, { - "ArchStdEvent": "DP_SPEC", + "ArchStdEvent": "DP_SPEC" }, { - "ArchStdEvent": "ASE_SPEC", + "ArchStdEvent": "ASE_SPEC" }, { - "ArchStdEvent": "VFP_SPEC", + "ArchStdEvent": "VFP_SPEC" }, { - "ArchStdEvent": "PC_WRITE_SPEC", + "ArchStdEvent": "PC_WRITE_SPEC" }, { - "ArchStdEvent": "CRYPTO_SPEC", + "ArchStdEvent": "CRYPTO_SPEC" }, { - "ArchStdEvent": "BR_IMMED_SPEC", + "ArchStdEvent": "BR_IMMED_SPEC" }, { - "ArchStdEvent": "BR_RETURN_SPEC", + "ArchStdEvent": "BR_RETURN_SPEC" }, { - "ArchStdEvent": "BR_INDIRECT_SPEC", + "ArchStdEvent": "BR_INDIRECT_SPEC" }, { - "ArchStdEvent": "ISB_SPEC", + "ArchStdEvent": "ISB_SPEC" }, { - "ArchStdEvent": "DSB_SPEC", + "ArchStdEvent": "DSB_SPEC" }, { - "ArchStdEvent": "DMB_SPEC", + "ArchStdEvent": "DMB_SPEC" }, { - "ArchStdEvent": "EXC_UNDEF", + "ArchStdEvent": "EXC_UNDEF" }, { - "ArchStdEvent": "EXC_SVC", + "ArchStdEvent": "EXC_SVC" }, { - "ArchStdEvent": "EXC_PABORT", + "ArchStdEvent": "EXC_PABORT" }, { - "ArchStdEvent": "EXC_DABORT", + "ArchStdEvent": "EXC_DABORT" }, { - "ArchStdEvent": "EXC_IRQ", + "ArchStdEvent": "EXC_IRQ" }, { - "ArchStdEvent": "EXC_FIQ", + "ArchStdEvent": "EXC_FIQ" }, { - "ArchStdEvent": "EXC_SMC", + "ArchStdEvent": "EXC_SMC" }, { - "ArchStdEvent": "EXC_HVC", + "ArchStdEvent": "EXC_HVC" }, { - "ArchStdEvent": "EXC_TRAP_PABORT", + "ArchStdEvent": "EXC_TRAP_PABORT" }, { - "ArchStdEvent": "EXC_TRAP_DABORT", + "ArchStdEvent": "EXC_TRAP_DABORT" }, { - "ArchStdEvent": "EXC_TRAP_OTHER", + "ArchStdEvent": "EXC_TRAP_OTHER" }, { - "ArchStdEvent": "EXC_TRAP_IRQ", + "ArchStdEvent": "EXC_TRAP_IRQ" }, { - "ArchStdEvent": "EXC_TRAP_FIQ", + "ArchStdEvent": "EXC_TRAP_FIQ" }, { - "ArchStdEvent": "RC_LD_SPEC", + "ArchStdEvent": "RC_LD_SPEC" }, { - "ArchStdEvent": "RC_ST_SPEC", - }, + "ArchStdEvent": "RC_ST_SPEC" + } ] diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json index 6328828c018c..d0a19866563d 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -154,297 +154,297 @@ "EventCode": "0x61", "EventName": "BUS_ACCESS_WR", "BriefDescription": "Bus access write" - } + }, { "PublicDescription": "Bus access, Normal, Cacheable, Shareable", "EventCode": "0x62", "EventName": "BUS_ACCESS_SHARED", "BriefDescription": "Bus access, Normal, Cacheable, Shareable" - } + }, { "PublicDescription": "Bus access, not Normal, Cacheable, Shareable", "EventCode": "0x63", "EventName": "BUS_ACCESS_NOT_SHARED", "BriefDescription": "Bus access, not Normal, Cacheable, Shareable" - } + }, { "PublicDescription": "Bus access, Normal", "EventCode": "0x64", "EventName": "BUS_ACCESS_NORMAL", "BriefDescription": "Bus access, Normal" - } + }, { "PublicDescription": "Bus access, peripheral", "EventCode": "0x65", "EventName": "BUS_ACCESS_PERIPH", "BriefDescription": "Bus access, peripheral" - } + }, { "PublicDescription": "Data memory access, read", "EventCode": "0x66", "EventName": "MEM_ACCESS_RD", "BriefDescription": "Data memory access, read" - } + }, { "PublicDescription": "Data memory access, write", "EventCode": "0x67", "EventName": "MEM_ACCESS_WR", "BriefDescription": "Data memory access, write" - } + }, { "PublicDescription": "Unaligned access, read", "EventCode": "0x68", "EventName": "UNALIGNED_LD_SPEC", "BriefDescription": "Unaligned access, read" - } + }, { "PublicDescription": "Unaligned access, write", "EventCode": "0x69", "EventName": "UNALIGNED_ST_SPEC", "BriefDescription": "Unaligned access, write" - } + }, { "PublicDescription": "Unaligned access", "EventCode": "0x6a", "EventName": "UNALIGNED_LDST_SPEC", "BriefDescription": "Unaligned access" - } + }, { "PublicDescription": "Exclusive operation speculatively executed, LDREX or LDX", "EventCode": "0x6c", "EventName": "LDREX_SPEC", "BriefDescription": "Exclusive operation speculatively executed, LDREX or LDX" - } + }, { "PublicDescription": "Exclusive operation speculatively executed, STREX or STX pass", "EventCode": "0x6d", "EventName": "STREX_PASS_SPEC", "BriefDescription": "Exclusive operation speculatively executed, STREX or STX pass" - } + }, { "PublicDescription": "Exclusive operation speculatively executed, STREX or STX fail", "EventCode": "0x6e", "EventName": "STREX_FAIL_SPEC", "BriefDescription": "Exclusive operation speculatively executed, STREX or STX fail" - } + }, { "PublicDescription": "Exclusive operation speculatively executed, STREX or STX", "EventCode": "0x6f", "EventName": "STREX_SPEC", "BriefDescription": "Exclusive operation speculatively executed, STREX or STX" - } + }, { "PublicDescription": "Operation speculatively executed, load", "EventCode": "0x70", "EventName": "LD_SPEC", "BriefDescription": "Operation speculatively executed, load" - } + }, { - "PublicDescription": "Operation speculatively executed, store" + "PublicDescription": "Operation speculatively executed, store", "EventCode": "0x71", "EventName": "ST_SPEC", "BriefDescription": "Operation speculatively executed, store" - } + }, { "PublicDescription": "Operation speculatively executed, load or store", "EventCode": "0x72", "EventName": "LDST_SPEC", "BriefDescription": "Operation speculatively executed, load or store" - } + }, { "PublicDescription": "Operation speculatively executed, integer data processing", "EventCode": "0x73", "EventName": "DP_SPEC", "BriefDescription": "Operation speculatively executed, integer data processing" - } + }, { "PublicDescription": "Operation speculatively executed, Advanced SIMD instruction", "EventCode": "0x74", "EventName": "ASE_SPEC", - "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction", - } + "BriefDescription": "Operation speculatively executed, Advanced SIMD instruction" + }, { "PublicDescription": "Operation speculatively executed, floating-point instruction", "EventCode": "0x75", "EventName": "VFP_SPEC", "BriefDescription": "Operation speculatively executed, floating-point instruction" - } + }, { "PublicDescription": "Operation speculatively executed, software change of the PC", "EventCode": "0x76", "EventName": "PC_WRITE_SPEC", "BriefDescription": "Operation speculatively executed, software change of the PC" - } + }, { "PublicDescription": "Operation speculatively executed, Cryptographic instruction", "EventCode": "0x77", "EventName": "CRYPTO_SPEC", "BriefDescription": "Operation speculatively executed, Cryptographic instruction" - } + }, { - "PublicDescription": "Branch speculatively executed, immediate branch" + "PublicDescription": "Branch speculatively executed, immediate branch", "EventCode": "0x78", "EventName": "BR_IMMED_SPEC", "BriefDescription": "Branch speculatively executed, immediate branch" - } + }, { - "PublicDescription": "Branch speculatively executed, procedure return" + "PublicDescription": "Branch speculatively executed, procedure return", "EventCode": "0x79", "EventName": "BR_RETURN_SPEC", "BriefDescription": "Branch speculatively executed, procedure return" - } + }, { - "PublicDescription": "Branch speculatively executed, indirect branch" + "PublicDescription": "Branch speculatively executed, indirect branch", "EventCode": "0x7a", "EventName": "BR_INDIRECT_SPEC", "BriefDescription": "Branch speculatively executed, indirect branch" - } + }, { - "PublicDescription": "Barrier speculatively executed, ISB" + "PublicDescription": "Barrier speculatively executed, ISB", "EventCode": "0x7c", "EventName": "ISB_SPEC", "BriefDescription": "Barrier speculatively executed, ISB" - } + }, { - "PublicDescription": "Barrier speculatively executed, DSB" + "PublicDescription": "Barrier speculatively executed, DSB", "EventCode": "0x7d", "EventName": "DSB_SPEC", "BriefDescription": "Barrier speculatively executed, DSB" - } + }, { - "PublicDescription": "Barrier speculatively executed, DMB" + "PublicDescription": "Barrier speculatively executed, DMB", "EventCode": "0x7e", "EventName": "DMB_SPEC", "BriefDescription": "Barrier speculatively executed, DMB" - } + }, { - "PublicDescription": "Exception taken, Other synchronous" + "PublicDescription": "Exception taken, Other synchronous", "EventCode": "0x81", "EventName": "EXC_UNDEF", "BriefDescription": "Exception taken, Other synchronous" - } + }, { - "PublicDescription": "Exception taken, Supervisor Call" + "PublicDescription": "Exception taken, Supervisor Call", "EventCode": "0x82", "EventName": "EXC_SVC", "BriefDescription": "Exception taken, Supervisor Call" - } + }, { - "PublicDescription": "Exception taken, Instruction Abort" + "PublicDescription": "Exception taken, Instruction Abort", "EventCode": "0x83", "EventName": "EXC_PABORT", "BriefDescription": "Exception taken, Instruction Abort" - } + }, { - "PublicDescription": "Exception taken, Data Abort and SError" + "PublicDescription": "Exception taken, Data Abort and SError", "EventCode": "0x84", "EventName": "EXC_DABORT", "BriefDescription": "Exception taken, Data Abort and SError" - } + }, { - "PublicDescription": "Exception taken, IRQ" + "PublicDescription": "Exception taken, IRQ", "EventCode": "0x86", "EventName": "EXC_IRQ", "BriefDescription": "Exception taken, IRQ" - } + }, { - "PublicDescription": "Exception taken, FIQ" + "PublicDescription": "Exception taken, FIQ", "EventCode": "0x87", "EventName": "EXC_FIQ", "BriefDescription": "Exception taken, FIQ" - } + }, { - "PublicDescription": "Exception taken, Secure Monitor Call" + "PublicDescription": "Exception taken, Secure Monitor Call", "EventCode": "0x88", "EventName": "EXC_SMC", "BriefDescription": "Exception taken, Secure Monitor Call" - } + }, { - "PublicDescription": "Exception taken, Hypervisor Call" + "PublicDescription": "Exception taken, Hypervisor Call", "EventCode": "0x8a", "EventName": "EXC_HVC", "BriefDescription": "Exception taken, Hypervisor Call" - } + }, { - "PublicDescription": "Exception taken, Instruction Abort not taken locally" + "PublicDescription": "Exception taken, Instruction Abort not taken locally", "EventCode": "0x8b", "EventName": "EXC_TRAP_PABORT", "BriefDescription": "Exception taken, Instruction Abort not taken locally" - } + }, { - "PublicDescription": "Exception taken, Data Abort or SError not taken locally" + "PublicDescription": "Exception taken, Data Abort or SError not taken locally", "EventCode": "0x8c", "EventName": "EXC_TRAP_DABORT", "BriefDescription": "Exception taken, Data Abort or SError not taken locally" - } + }, { - "PublicDescription": "Exception taken, Other traps not taken locally" + "PublicDescription": "Exception taken, Other traps not taken locally", "EventCode": "0x8d", "EventName": "EXC_TRAP_OTHER", |