diff options
| author | Owen Chen <owen.chen@mediatek.com> | 2019-03-05 13:05:40 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-11 13:13:08 -0700 |
| commit | 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb (patch) | |
| tree | c64502c6a88052a8b1857af5516b68af1d461f8d /drivers/clk/mediatek/clk-mtk.h | |
| parent | a3ae549917f1634f85c62984617521801505eb1e (diff) | |
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The PLL frequency lower-bound is vary from 1GHz to
1.5GHz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.h')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index fb27b5bf30d9..9d53ee3dffd2 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -227,8 +227,10 @@ struct mtk_pll_data { unsigned int flags; const struct clk_ops *ops; u32 rst_bar_mask; + unsigned long fmin; unsigned long fmax; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; |