From 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb Mon Sep 17 00:00:00 2001 From: Owen Chen Date: Tue, 5 Mar 2019 13:05:40 +0800 Subject: clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data 1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits, add a variable to indicate this change and backward-compatible. 2. fmin: The PLL frequency lower-bound is vary from 1GHz to 1.5GHz, add a variable to indicate platform-dependent. Signed-off-by: Owen Chen Signed-off-by: Weiyi Lu Acked-by: Sean Wang Reviewed-by: James Liao Reviewed-by: Nicolas Boichat Tested-by: Nicolas Boichat Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/mediatek/clk-mtk.h') diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index fb27b5bf30d9..9d53ee3dffd2 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -227,8 +227,10 @@ struct mtk_pll_data { unsigned int flags; const struct clk_ops *ops; u32 rst_bar_mask; + unsigned long fmin; unsigned long fmax; int pcwbits; + int pcwibits; uint32_t pcw_reg; int pcw_shift; const struct mtk_pll_div_table *div_table; -- cgit v1.2.3