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2023-03-02Take into account the `cpufreq_unregister_driver` prototype change1.95.5CyrIng
2023-03-02[CR] Place empty statement to fix build with older compilerCyrIng
2023-02-18[Intel 11th to 14th gen] Convert DRAM Speed to MT/s1.95.4CyrIng
2023-02-18[Intel 11th to 14th gen] Compute Bus Rate based on BIOS MC PLLCyrIng
2023-02-17[Intel][Airmont] Fixed the Bus and DRAM frequency rates (#399)1.95.3CyrIng
2023-02-14[Intel 11th to 14th gen] Monitor SA voltage when ARCH_PMC=PCU builtCyrIng
2023-02-14[Intel][Core i7-12700H] Attempt to decode TCO WatchdogCyrIng
2023-02-14[Intel:up to 13th gen] Attempt to probe the interleaved controllersCyrIng
2023-02-12[Intel] Introducing Spreadtrum as an Airmont architectureCyrIng
2023-02-09[Intel] Improving the Airmont IMC geometryCyrIng
2023-02-05[Intel][Airmont][Silvermont] Attempt to decode `tCKE` from DRMC1.95.2CyrIng
2023-02-05[Intel][Airmont] Adding a new IMC decoder (DRAM timings)CyrIng
2023-02-04[UI] Fixing the aggregation of the minimum ratioCyrIng
2023-02-04[Intel] Adding the Emerald Rapids architecture entryCyrIng
2023-02-02[Intel] Fixed misspelled RKEN (Rank Enabled)CyrIng
2023-01-31[AMD][Zen] Debugging a thermal reset which messes the highest limitCyrIng
2023-01-28[CR] Removed the implicit `KERN_INFO` in `pr_info()`CyrIng
2023-01-28[Intel] MSR registers which increment at the same rate as the TSC.CyrIng
2023-01-28[Intel] from SKL to ADL: aggregate `tRCD_WR` DRAM timingCyrIng
2023-01-26[UI] Show the DDR5 `RCDw` timing of Intel IMCCyrIng
2023-01-26[Intel][RPL] [De]Activate the MSR Uncore counter.CyrIng
2023-01-26[AMD][Zen] Specified CpuidUserDis bit in HWCR (CPUID User Disable)CyrIng
2023-01-25[AMD] "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenamesCyrIng
2023-01-22Version 1.95.11.95.1CyrIng
2023-01-22[UI] Split `tREFI` in two cells in `Timing_DDR4`CyrIng
2023-01-22[Intel] ODCM can now be [de]activated on Raptor Lake processors.CyrIng
2023-01-22[CLI][JSON] Rename `tRCD` with `tRCD_R` and add `tRCD_W`CyrIng
2023-01-22[Intel][ADL][RPL] Possible `tRCD_WR` timing with DDR5 (JSON)CyrIng
2023-01-22[Intel][ADL][RPL] Based on DDR gen: compute Size and ControllersCyrIng
2023-01-22[Intel][RPL] Changed the voltage scope to Core.CyrIng
2023-01-21[Intel] Merge and complete ADL and RPL Processor & Chipset IDsCyrIng
2023-01-20[UI] Raised the ratio range up to the Uncore max ratio (issue #405)CyrIng
2023-01-19[Intel] Attempt to decode the Raptor Lake IMCCyrIng
2023-01-19Based on Raptor Lake, raise `MAX_FREQ_HZ` up to 7125000000 HertzCyrIng
2023-01-19Assignment fix of Mobile {Coffee Lake, Kaby Lake} codenames (#401)CyrIng
2023-01-18Fix the wrong unit used for RAM Maximum Capacity (issue #403)CyrIng
2023-01-18[CLI] Added the SYSCFG System Register into the the JSON exportCyrIng
2023-01-16[Doc] Specified values range of Skylake IMC timingsCyrIng
2023-01-15[AMD64] System-Configuration Register (SYSCFG)CyrIng
2023-01-14[Intel][Airmont] Fixed the list of processors belonging to BraswellCyrIng
2023-01-14[AMD] Adding specifics for "AMD EPYC 9654"CyrIng
2023-01-12[AMD][Zen][UMC] BIOS Transparent SME (TSME)CyrIng
2023-01-11[AMD][Zen][UMC] BIOS state of the DRAM Data ScramblingCyrIng
2023-01-10Version 1.95CyrIng
2023-01-07[UI] Performance Capabilities window size based on `HWP|CPPC` avail1.94.4CyrIng
2023-01-06[AMD] Adding specifics for "Barcelo R" and "Rembrandt R"CyrIng
2023-01-06[Doc] Update the Kernel optional `CONFIG_` directives list.1.94.3CyrIng
2023-01-06[CR] Includes ACPI header files to fix build with Debian 4.9.0-19CyrIng
2023-01-06[AMD][Raphael] 7950X3D, 7900X3D, 7800X3D, 7900, 7700, 76001.94.2CyrIng
2023-01-06[UI] Adding comments to the EEO and R2H technologiesCyrIng
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