CoreFreq version 1.861.86

21 files changed, 9103 insertions, 6028 deletions

diff --git a/README.md b/README.md
index 6a8ae8c..cb55585 100644
--- a/README.md
+++ b/README.md
@@ -436,7 +436,10 @@ parm:           IOMWAIT_Enable:I/O MWAIT Redirection Enable (short)
 parm:           CStateIORedir:Power Mgmt IO Redirection C-State (short)
 parm:           Config_TDP_Level:Config TDP Control Level (short)
 parm:           Custom_TDP_Offset:TDP Limit Offset (watt) (array of short)
-parm:           Activate_TDP_Limit:Activate TDP Limit (array of short)
+parm:           Activate_TDP_Limit:Activate TDP Limiting (array of short)
+parm:           Activate_TDP_Clamp:Activate TDP Clamping (array of short)
+parm:           Custom_TDC_Offset:TDC Limit Offset (amp) (short)
+parm:           Activate_TDC_Limit:Activate TDC Limiting (short)
 parm:           L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short)
 parm:           L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short)
 parm:           L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short)
@@ -476,6 +479,7 @@ parm:           Mech_STIBP:Mitigation Mechanism STIBP (short)
 parm:           Mech_SSBD:Mitigation Mechanism SSBD (short)
 parm:           Mech_IBPB:Mitigation Mechanism IBPB (short)
 parm:           Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short)
+parm:           WDT_Enable:Watchdog Hardware Timer (short)
 ```  
 
 ## Algorithm
diff --git a/amdmsr.h b/amdmsr.h
index 07135c3..fd62497 100644
--- a/amdmsr.h
+++ b/amdmsr.h
@@ -54,6 +54,8 @@
 	#define MSR_AMD_CSTATE_BAR		0xc0010073
 #endif
 
+#define MSR_AMD_CPU_WDT_CFG			0xc0010074
+
 #ifndef MSR_VM_CR
 	#define MSR_VM_CR			0xc0010114
 #endif
@@ -113,6 +115,9 @@
 #define SMU_AMD_INDEX_REGISTER_F17H	PCI_CONFIG_ADDRESS(0, 0, 0, 0x60)
 #define SMU_AMD_DATA_REGISTER_F17H	PCI_CONFIG_ADDRESS(0, 0, 0, 0x64)
 
+#define SMU_AMD_INDEX_REGISTER_HSMP	PCI_CONFIG_ADDRESS(0, 0, 0, 0xc4)
+#define SMU_AMD_DATA_REGISTER_HSMP	PCI_CONFIG_ADDRESS(0, 0, 0, 0xc8)
+
 /* Sources:
  * BKDG for AMD Family [15_60h - 15_70h]
 	D0F0xBC_xD820_0CA4 Reported Temperature Control
@@ -145,6 +150,44 @@
 	#define MSR_AMD_CC6_F17H_STATUS 	0xc0010296
 #endif
 
+/* Sources: PPR Vol 2 for AMD Family 19h Model 01h B1			*/
+#define SMU_HSMP_F19H	/*Cmd:*/0x3b10534, /*Arg:*/0x3b109e0, /*Rsp:*/0x3b10980
+
+enum HSMP_FUNC {
+	HSMP_TEST_MSG	= 0x1,	/* Returns [ARG0] + 1			*/
+	HSMP_RD_SMU_VER = 0x2,	/* SMU FW Version			*/
+	HSMP_RD_VERSION = 0x3,	/* Interface Version			*/
+	HSMP_RD_CUR_PWR = 0x4,	/* Current Socket power (mWatts)	*/
+	HSMP_WR_PKG_PL1 = 0x5,	/* Input within [31:0]; Limit (mWatts)	*/
+	HSMP_RD_PKG_PL1 = 0x6,	/* Returns Socket power limit (mWatts)	*/
+	HSMP_RD_MAX_PPT = 0x7,	/* Max Socket power limit (mWatts)	*/
+	HSMP_WR_SMT_BOOST=0x8,	/* ApicId[31:16], Max Freq. (MHz)[15:0] */
+	HSMP_WR_ALL_BOOST=0x9,	/* Max Freq. (MHz)[15:0] for ALL	*/
+	HSMP_RD_SMT_BOOST=0xa,	/* Input ApicId[15:0]; Dflt Fmax[15:0]	*/
+	HSMP_RD_PROCHOT = 0xb,	/* 1 = PROCHOT is asserted		*/
+	HSMP_WR_XGMI_WTH= 0xc,	/* 0 = x2, 1 = x8, 2 = x16		*/
+	HSMP_RD_APB_PST = 0xd,	/* Data Fabric P-state[7-0]={0,1,2,3}	*/
+	HSMP_ENABLE_APB = 0xe,	/* Data Fabric P-State Performance Boost*/
+	HSMP_RD_DF_MCLK = 0xf,	/* FCLK[ARG:0], MEMCLK[ARG:1] (MHz)	*/
+	HSMP_RD_CCLK	= 0x10, /* CPU core clock limit (MHz)		*/
+	HSMP_RD_PC0	= 0x11, /* Socket C0 Residency (100%)		*/
+	HSMP_WR_DPM_LCLK= 0x12, /* NBIO[24:16]; Max[15:8], Min[7:0] DPM */
+	HSMP_RESERVED	= 0x13,
+	HSMP_RD_DDR_BW	= 0x14	/* Max[31:20];Usage{Gbps[19:8],Pct[7:0]}*/
+};
+
+enum {
+	HSMP_UNSPECIFIED= 0x0,
+	HSMP_RESULT_OK	= 0x1,
+	HSMP_FAIL_BGN	= 0x2,
+	HSMP_FAIL_END	= 0xfd,
+	HSMP_INVAL_MSG	= 0xfe,
+	HSMP_INVAL_INPUT= 0xff
+};
+
+#define IS_HSMP_OOO(_rx) (_rx == HSMP_UNSPECIFIED			\
+			|| (_rx >= HSMP_FAIL_BGN && _rx <= HSMP_FAIL_END))
+
 /* Sources: PPR for AMD Family 17h					*/
 #define AMD_FCH_PM_CSTATE_EN	0x0000007e
 
@@ -321,14 +364,17 @@ typedef union
 	IoCfgGpFault	: 21-20,
 	LockTscToCurrP0 : 22-21,/* RW:lock the TSC to the current P0 frequency*/
 	Reserved6	: 24-22,
-	TscFreqSel	: 25-24,
-	CpbDis		: 26-25,
-	EffFreqCntMwait : 27-26,
-	EffFreqROLock	: 28-27,
+	TscFreqSel	: 25-24, /* RO: 1=TSC increments at the P0 frequency */
+	CpbDis		: 26-25, /* RW: 1=Core Performance Boost disable */
+	EffFreqCntMwait : 27-26, /* RW: A-M-Perf increment during MWAIT */
+	EffFreqROLock	: 28-27, /* W1: Lock A-M-Perf & IR-Perf counters */
 	Reserved7	: 29-28,
 	CSEnable	: 30-29,
 	IRPerfEn	: 31-30, /* RW: enable instructions retired counter */
-	Reserved	: 64-31;
+	Reserved8	: 32-31,
+	Undefined	: 33-32, /* RW: enable by default		*/
+	SmmPgCfgLock	: 34-33,
+	Reserved9	: 64-34;
     } Family_17h;
     struct
     {
@@ -910,6 +956,20 @@ typedef union
 
 typedef union
 {
+	unsigned long long value;
+    struct
+    {
+	unsigned long long	 /* Per Core: MSR 0xC0010074 (RW)	*/
+	TmrCfgEn	:  1-0,
+	TmrTimebaseSel	:  3-1,
+	Reserved1	:  7-3,
+	TmrCfgSeverity	: 10-7,
+	Reserved2	: 64-10;
+    };
+} AMD_CPU_WDT_CFG;
+
+typedef union
+{
 	unsigned int		value;
 	struct
 	{
diff --git a/corefreq-api.h b/corefreq-api.h
index c452204..4e774b3 100644
--- a/corefreq-api.h
+++ b/corefreq-api.h
@@ -678,12 +678,10 @@ typedef struct
 
 
 typedef struct {
-		OS_DRIVER	OS;
-
 		int		taskCount;
 		TASK_MCB	taskList[TASK_LIMIT];
 
-		MEM_MCB		memInfo;
+		MEM_MCB 	memInfo;
 
 		unsigned int	kernelVersionNumber;
 
@@ -762,6 +760,7 @@ typedef struct
 	BitCC	/* AMD */	PC6_Mask __attribute__ ((aligned (16)));
 	BitCC			SPEC_CTRL_Mask __attribute__ ((aligned (16)));
 	BitCC			ARCH_CAP_Mask  __attribute__ ((aligned (16)));
+	BitCC			WDT_Mask __attribute__ ((aligned (16)));
 
 	enum THERMAL_FORMULAS	thermalFormula;
 	enum VOLTAGE_FORMULAS	voltageFormula;
@@ -801,18 +800,21 @@ typedef struct
 		RAPL_POWER_UNIT Unit;
 	  union {
 	    struct {
-/*32-bits*/	unsigned int		_rsv32;
+/*64-bits*/	DOMAIN_POWER_LIMIT	PowerLimit[PWR_DOMAIN(SIZE)];
+/*64-bits*/	DOMAIN_POWER_INFO	PowerInfo;
+/*32-bits*/	struct {
+			unsigned int	TDC	:  1-0,
+					_Unused : 32-1;
+		} Enable_Limit;
 /*16-bits*/	unsigned short		EDC;
 /*16-bits*/	unsigned short		TDC;
-/*64-bits*/	DOMAIN_POWER_INFO	PowerInfo;
-/*64-bits*/	DOMAIN_POWER_LIMIT	PowerLimit[PWR_DOMAIN(SIZE)];
 	    };
 	    struct {
+/*64-bits*/	unsigned long long	_pad64[PWR_DOMAIN(SIZE)];
 /*32-bits*/	AMD_17_MTS_CPK_PWR	PWR;
 /*32-bits*/	AMD_17_MTS_CPK_TDP	TDP;
 /*32-bits*/	AMD_17_MTS_CPK_EDC	EDC;
 /*32-bits*/	unsigned int		_pad32;
-/*64-bits*/	unsigned long long	_pad64[PWR_DOMAIN(SIZE)];
 	    } Zen;
 	  };
 	} PowerThermal;
@@ -822,7 +824,9 @@ typedef struct
 			size_t	Size;
 			int	Order;
 		} ReqMem;
-	} OS;
+	} Gate;
+
+	OS_DRIVER		OS;
 
 	struct {
 		Bit64		NMI;
@@ -880,6 +884,7 @@ typedef struct
 	BitCC			PSCHANGE_MC_NO	__attribute__ ((aligned (16)));
 	BitCC			TAA_NO		__attribute__ ((aligned (16)));
 	BitCC			SPLA		__attribute__ ((aligned (16)));
+	BitCC			WDT		__attribute__ ((aligned (16)));
 
 	struct {
 		Bit64		Signal	__attribute__ ((aligned (8)));
@@ -1042,6 +1047,8 @@ typedef struct
 #ifndef PCI_DEVICE_ID_INTEL_NHM_EP_NON_CORE
 	#define PCI_DEVICE_ID_INTEL_NHM_EP_NON_CORE	0x2c70
 #endif
+/* Source: Intel Using the Intel ICH Family Watchdog Timer (WDT)	*/
+#define PCI_DEVICE_ID_INTEL_ICH10_LPC			0x3a16
 /* Source: Intel X58 Express Chipset Datasheet				*/
 #define PCI_DEVICE_ID_INTEL_X58_HUB_CORE		0x342e
 #define PCI_DEVICE_ID_INTEL_X58_HUB_CTRL		0x3423
diff --git a/corefreq-cli-json.c b/corefreq-cli-json.c
index f4363ac..085ab4a 100644
--- a/corefreq-cli-json.c
+++ b/corefreq-cli-json.c
@@ -16,6 +16,7 @@
 #include "coretypes.h"
 #include "corefreq.h"
 #include "corefreq-ui.h"
+#include "corefreq-cli-rsc.h"
 #include "corefreq-cli.h"
 #include "corefreq-cli-json.h"
 #include "corefreq-cli-extra.h"
@@ -1306,6 +1307,8 @@ void JsonSysInfo(SHM_STRUCT *Shm, CELL_FUNC OutFunc)
 			json_literal(&s, "%llu", Shm->Proc.Technology.PC6);
 			json_key(&s, "SMM");
 			json_literal(&s, "%llu", Shm->Proc.Technology.SMM);
+			json_key(&s, "WDT");
+			json_literal(&s, "%llu", Shm->Proc.Technology.WDT);
 			json_key(&s, "VM");
 			json_literal(&s, "%llu", Shm->Proc.Technology.VM);
 			json_key(&s, "IOMMU");
diff --git a/corefreq-cli-rsc-en.h b/corefreq-cli-rsc-en.h
index 3018b3d..3184e12 100644
--- a/corefreq-cli-rsc-en.h
+++ b/corefreq-cli-rsc-en.h
@@ -4,21 +4,68 @@
  * Licenses: GPL2
  */
 
-#define RSC_COPY_R0_EN "      by CyrIng                                     "
-#define RSC_COPY_R1_EN "                                                    "
-#define RSC_COPY_R2_EN "            (C)2015-2021 CYRIL INGENIERIE           "
+#define RSC_COPY0_CODE_EN "      by CyrIng                                     "
+#define RSC_COPY1_CODE_EN "                                                    "
+#define RSC_COPY2_CODE_EN "            (C)2015-2021 CYRIL INGENIERIE           "
 
 #define RSC_LAYOUT_HEADER_PROC_CODE_EN					\
 {									\
 	' ','P','r','o','c','e','s','s','o','r',' ','[' 		\
 }
 
+#define RSC_LAYOUT_HEADER_CPU_CODE_EN					\
+{									\
+	']',' ',' ',' ',' ','/',' ',' ',' ',' ','C','P','U'		\
+}
+
+#define RSC_LAYOUT_HEADER_ARCH_CODE_EN					\
+{									\
+	' ','A','r','c','h','i','t','e','c','t','u','r','e',' ','['	\
+}
+
+#define RSC_LAYOUT_HEADER_CACHE_L1_CODE_EN				\
+{									\
+	']',' ','C','a','c','h','e','s',' ',				\
+	'L','1',' ','I','n','s','t','=',' ',' ',' ',			\
+	'D','a','t','a','=',' ',' ',' ','K','B' 			\
+}
+
 #define RSC_LAYOUT_HEADER_BCLK_CODE_EN					\
 {									\
 	' ','B','a','s','e',' ','C','l','o','c','k',' ',		\
 	'~',' ','0','0','0',',','0','0','0',',','0','0','0',' ','H','z' \
 }
 
+#define RSC_LAYOUT_HEADER_CACHES_CODE_EN				\
+{									\
+	'L','2','=',' ',' ',' ',' ',' ',' ',' ',			\
+	'L','3','=',' ',' ',' ',' ',' ',' ','K','B'			\
+}
+
+#define RSC_LAYOUT_RULER_LOAD_CODE_EN					\
+{									\
+	'-','-','-',' ', '!',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
 #define RSC_LAYOUT_RULER_REL_LOAD_CODE_EN				\
 {									\
 	'R','e','l','a','t','i','v','e',' ','f','r','e','q','u','e','n',\
@@ -31,6 +78,67 @@
 	'c','y' 							\
 }
 
+#define RSC_LAYOUT_MONITOR_FREQUENCY_CODE_EN				\
+{									\
+	' ',' ',' ',' ',' ',0x0,' ',' ',' ',0x0,' ',' ',0x0,' ',' ',0x0,\
+	' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\
+	' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\
+	' ',' ',' ',' ',0x0,' ',' ',0x0,' ',' ',' ',' ',0x0,' ',' ',0x0,\
+	' ',' ',' ',' ',' ',0x0,' ',' ',' ',0x0,' ',' ',' '		\
+}
+
+#define RSC_LAYOUT_MONITOR_INST_CODE_EN					\
+{									\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',0x0,' ',' ',' ',' ',\
+	' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',0x0,' ',\
+	' ',' ',' ',' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',0x0,' ',' ',' ',' ',' ',' ',0x0,0x0,' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '		\
+}
+
+#define RSC_LAYOUT_MONITOR_COMMON_CODE_EN				\
+{									\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '		\
+}
+
+#define RSC_LAYOUT_MONITOR_TASKS_CODE_EN				\
+{									\
+	' ',' ',' ',' ',' ',0x0,' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \
+}
+
+#define RSC_LAYOUT_MONITOR_SLICE_CODE_EN				\
+{									\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' '	\
+}
+
 #define RSC_LAYOUT_RULER_FREQUENCY_CODE_EN				\
 {									\
 	'-','-','-',' ','F','r','e','q','(','M','H','z',')',' ','R','a',\
@@ -79,6 +187,126 @@
 	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
 }
 
+#define RSC_LAYOUT_RULER_FREQUENCY_PKG_CODE_EN				\
+{									\
+	'%',' ','P','k','g',' ','[',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',']',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
+#define RSC_LAYOUT_RULER_INST_CODE_EN					\
+{									\
+	'-','-','-','-','-','-','-','-','-','-','-','-',' ','I','P','S',\
+	' ','-','-','-','-','-','-','-','-','-','-','-','-','-','-',' ',\
+	'I','P','C',' ','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-',' ','C','P','I',' ','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-',' ','I','N','S','T',' ','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
+#define RSC_LAYOUT_RULER_CYCLES_CODE_EN 				\
+{									\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-',' ','C',\
+	'0',':','U','C','C',' ','-','-','-','-','-','-','-','-','-','-',\
+	' ','C','0',':','U','R','C',' ','-','-','-','-','-','-','-','-',\
+	'-','-','-','-',' ','C','1',' ','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-',' ','T','S','C',' ','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
+#define RSC_LAYOUT_RULER_CSTATES_CODE_EN				\
+{									\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	' ','C','1',' ','-','-','-','-','-','-','-','-','-','-','-','-',\
+	' ','C','2',':','C','3',' ','-','-','-','-','-','-','-','-','-',\
+	'-','-',' ','C','4',':','C','6',' ','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-',' ','C','7',' ','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
+#define RSC_LAYOUT_RULER_INTERRUPTS_CODE_EN				\
+{									\
+	'-','-','-','-','-','-','-','-','-','-',' ','S','M','I',' ','-',\
+	'-','-','-','-','-','-','-','-','-','-','-',' ','N','M','I','[',\
+	' ','L','O','C','A','L',' ',' ',' ','U','N','K','N','O','W','N',\
+	' ',' ','P','C','I','_','S','E','R','R','#',' ',' ','I','O','_',\
+	'C','H','E','C','K',']',' ','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-',\
+	'-','-','-','-','-','-','-','-','-','-','-','-','-','-','-','-' \
+}
+
 #define RSC_LAYOUT_RULER_PACKAGE_CODE_EN				\
 	"------------ Cycles ---- State -------------------- TSC Rati"	\
 	"o ----------------------------------------------------------"	\
@@ -95,6 +323,64 @@
 	"------------------------------------------------------------"	\
 	"--------------------"
 
+#define RSC_LAYOUT_PACKAGE_PC_CODE_EN					\
+{									\
+	' ',' ','0','0',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \
+}
+
+#define RSC_LAYOUT_PACKAGE_PC02_CODE_EN {'P', 'C', '0', '2'}
+#define RSC_LAYOUT_PACKAGE_PC03_CODE_EN {'P', 'C', '0', '3'}
+#define RSC_LAYOUT_PACKAGE_PC04_CODE_EN {'P', 'C', '0', '4'}
+#define RSC_LAYOUT_PACKAGE_PC06_CODE_EN {'P', 'C', '0', '6'}
+#define RSC_LAYOUT_PACKAGE_PC07_CODE_EN {'P', 'C', '0', '7'}
+#define RSC_LAYOUT_PACKAGE_PC08_CODE_EN {'P', 'C', '0', '8'}
+#define RSC_LAYOUT_PACKAGE_PC09_CODE_EN {'P', 'C', '0', '9'}
+#define RSC_LAYOUT_PACKAGE_PC10_CODE_EN {'P', 'C', '1', '0'}
+#define RSC_LAYOUT_PACKAGE_MC06_CODE_EN {'M', 'C', '0', '6'}
+
+#define RSC_LAYOUT_PACKAGE_UNCORE_CODE_EN				\
+{									\
+	' ','T','S','C',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ','U','N','C','O','R','E',':',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
+	' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \
+}
+
 #define RSC_LAYOUT_TASKS_STATE_SORTED_CODE_EN				\
 {									\
 	'(','s','o','r','t','e','d',' ', 'b','y',			\
@@ -146,6 +432,16 @@
 	' ', 'V','a','l','u','e',' ','[',' ',' ',' ',']',' '		\
 }
 
+#define RSC_LAYOUT_TASKS_VALUE_OFF_CODE_EN				\
+{									\
+	'O','F','F'							\
+}
+
+#define RSC_LAYOUT_TASKS_VALUE_ON_CODE_EN				\
+{									\
+	' ','O','N'							\
+}
+
 #define RSC_LAYOUT_TASKS_TRACKING_CODE_EN				\
 {									\
 	' ','T','r','a','c','k','i', 'n','g',' ','P','I','D',' ','[',' ',\
@@ -176,7 +472,7 @@
 	"------------------------------------------------------------"	\
 	"--------------------"
 
-#define RSC_LAYOUT_RULER_PWR_PFM_CODE_EN				\
+#define RSC_LAYOUT_RULER_PWR_PLATFORM_CODE_EN				\
 	"-RAM:   .    ( ) Platform:   .    ( ) - Package:   .    ( ) "	\
 	"- Cores:   .    ( )-----------------------------------------"	\
 	"------------------------------------------------------------"	\
@@ -224,6 +520,30 @@
 	"------------------------------------------------------------"	\
 	"--------------------"
 
+#define RSC_LAYOUT_FOOTER_TECH_X86_CODE_EN				\
+{									\
+	'T','e','c','h',' ','[',' ',' ','T','S','C',' ',' ',',' 	\
+}
+
+#define RSC_LAYOUT_FOOTER_TECH_INTEL_CODE_EN				\
+{									\
+	'H','T','T',',','E','I','S','T',',','I','D','A',',',		\
+	'T','U','R','B','O',',','C','1','E',',',			\
+	' ','P','M',',','C','3','A',',','C','1','A',',',		\
+	'C','3','U',',','C','1','U',',',				\
+	'T','M',',','H','O','T',']',' ',				\
+	'V','[',' ','.',' ',' ',']',' ','T','[',' ',' ',' ',' ',']' 	\
+}
+
+#define RSC_LAYOUT_FOOTER_TECH_AMD_CODE_EN				\
+{									\
+	'S','M','T',',','C','n','Q',',','H','W','P',',',		\
+	'B','O','O','S','T',',','C','1','E',',','C','C','6',		\
+	',','P','C','6',',','C','C','x',',','D','T','S',',',		\
+	'T','T','P',',','H','O','T',']',' ',' ',' ',' ',' ',		\
+	'V','[',' ','.',' ',' ',']',' ','T','[',' ',' ',' ',' ',']' 	\
+}
+
 #define RSC_LAYOUT_FOOTER_SYSTEM_CODE_EN				\
 {									\
 	'T','a','s','k','s',' ','[',' ',' ',' ',' ',' ',' ',']',	\
@@ -231,10 +551,40 @@
 	' ','/',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','B',']' 	\
 }
 
-#define RSC_CREATE_HOTPLUG_CPU_ENABLE_CODE_EN	"<   ENABLE >"
-#define RSC_CREATE_HOTPLUG_CPU_DISABLE_CODE_EN	"<  DISABLE >"
-#define RSC_CREATE_HOTPLUG_CPU_ONLINE_CODE_EN	" %03u   On   "
-#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_CODE_EN	" %03u  Off   "
+#define RSC_LAYOUT_CARD_CORE_ONLINE_COND0_CODE_EN			\
+{									\
+	'[',' ',' ',' ',' ',' ',' ',' ',' ','C',' ',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_CORE_ONLINE_COND1_CODE_EN			\
+{									\
+	'[',' ',' ',' ',' ',' ',' ',' ',' ','F',' ',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_CORE_OFFLINE_CODE_EN				\
+{									\
+	'[',' ',' ',' ',' ',' ',' ','O','F','F',' ',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_CLK_CODE_EN					\
+{									\
+	'[',' ','0','0','0','.','0',' ','M','H','z',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_UNCORE_CODE_EN					\
+{									\
+	'[','U','N','C','O','R','E',' ',' ',' ',' ',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_BUS_CODE_EN					\
+{									\
+	'[','B','u','s',' ',' ',' ',' ',' ',' ',' ',']' 		\
+}
+
+#define RSC_LAYOUT_CARD_MC_CODE_EN					\
+{									\
+	'[',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',']' 		\
+}
 
 #define RSC_LAYOUT_CARD_LOAD_CODE_EN					\
 {									\
@@ -246,11 +596,21 @@
 	'[',' ',' ','%','I','D','L','E',' ',' ',' ',']' 		\
 }
 
+#define RSC_LAYOUT_CARD_RAM_CODE_EN					\
+{									\
+	'[',' ',' ',' ',' ',' ',' ','/',' ',' ',' ',']' 		\
+}
+
 #define RSC_LAYOUT_CARD_TASK_CODE_EN					\
 {									\
 	'[','T','a','s','k','s',' ',' ',' ',' ',' ',']' 		\
 }
 
+#define RSC_CREATE_HOTPLUG_CPU_ENABLE_CODE_EN	"<   ENABLE >"
+#define RSC_CREATE_HOTPLUG_CPU_DISABLE_CODE_EN	"<  DISABLE >"
+#define RSC_CREATE_HOTPLUG_CPU_ONLINE_CODE_EN	" %03u   On   "
+#define RSC_CREATE_HOTPLUG_CPU_OFFLINE_CODE_EN	" %03u  Off   "
+
 #define RSC_PROCESSOR_TITLE_CODE_EN	" Processor "
 #define RSC_PROCESSOR_CODE_EN		"Processor"
 #define RSC_ARCHITECTURE_CODE_EN	"Architecture"
@@ -287,7 +647,7 @@
 #define RSC_SCOPE_CORE_CODE_EN		"Core"
 #define RSC_SCOPE_PACKAGE_CODE_EN	" Pkg"
 
-#define RSC_CPUID_TITLE_EN		\
+#define RSC_CPUID_TITLE_CODE_EN 	\
 	" function           EAX          EBX          ECX          EDX "
 
 #define RSC_LARGEST_STD_FUNC_CODE_EN	"Largest Standard Function"
@@ -506,6 +866,7 @@
 #define RSC_TECHNOLOGIES_EEO_CODE_EN	"Energy Efficiency Optimization"
 #define RSC_TECHNOLOGIES_R2H_CODE_EN	"Race To Halt Optimization"
 #define RSC_TECHNOLOGIES_HYPERV_CODE_EN "Hypervisor"
+#define RSC_TECHNOLOGIES_WDT_CODE_EN	"Watchdog Timer"
 
 #define RSC_PERF_MON_TITLE_CODE_EN	" Performance Monitoring "
 #define RSC_VERSION_CODE_EN		"Version"
@@ -818,6 +1179,7 @@
 #define RSC_MENU_ITEM_KERNEL_CODE_EN		" Kernel data        [k] "
 #define RSC_MENU_ITEM_HOTPLUG_CODE_EN		" HotPlug CPU        [#] "
 #define RSC_MENU_ITEM_TOOLS_CODE_EN		" Tools              [O] "
+#define RSC_MENU_ITEM_THEME_CODE_EN		" Theme              [E] "
 #define RSC_MENU_ITEM_ABOUT_CODE_EN		" About              [a] "
 #define RSC_MENU_ITEM_HELP_CODE_EN		" Help               [h] "
 #define RSC_MENU_ITEM_KEYS_CODE_EN		" Shortcuts         [F1] "
@@ -825,16 +1187,16 @@
 #define RSC_MENU_ITEM_QUIT_CODE_EN		" Quit        [Ctrl]+[x] "
 #define RSC_MENU_ITEM_DASHBOARD_CODE_EN 	" Dashboard          [d] "
 #define RSC_MENU_ITEM_FREQUENCY_CODE_EN 	" Frequency          [f] "
-#define RSC_MENU_ITEM_INST_CYCLE_CODE_EN	" Inst cycles        [i] "
-#define RSC_MENU_ITEM_CORE_CYCLE_CODE_EN	" Core cycles        [c] "
-#define RSC_MENU_ITEM_IDLE_STATE_CODE_EN	" Idle C-States      [l] "
-#define RSC_MENU_ITEM_PKG_CYCLE_CODE_EN 	" Package cycles     [g] "
+#define RSC_MENU_ITEM_INST_CYCLES_CODE_EN	" Inst cycles        [i] "
+#define RSC_MENU_ITEM_CORE_CYCLES_CODE_EN	" Core cycles        [c] "
+#define RSC_MENU_ITEM_IDLE_STATES_CODE_EN	" Idle C-States      [l] "
+#define RSC_MENU_ITEM_PKG_CYCLES_CODE_EN	" Package cycles     [g] "
 #define RSC_MENU_ITEM_TASKS_MON_CODE_EN 	" Tasks Monitoring   [x] "
 #define RSC_MENU_ITEM_SYS_INTER_CODE_EN 	" System Interrupts  [q] "
 #define RSC_MENU_ITEM_SENSORS_CODE_EN		" Sensors            [C] "
 #define RSC_MENU_ITEM_VOLTAGE_CODE_EN		"   Voltage          [V] "
 #define RSC_MENU_ITEM_POWER_CODE_EN		"   Power            [W] "
-#define RSC_MENU_ITEM_SLICE_CTR_CODE_EN 	" Slice counters     [T] "
+#define RSC_MENU_ITEM_SLICE_CTRS_CODE_EN	" Slice counters     [T] "
 #define RSC_MENU_ITEM_PROCESSOR_CODE_EN 	" Processor          [p] "
 #define RSC_MENU_ITEM_TOPOLOGY_CODE_EN		" Topology           [m] "
 #define RSC_MENU_ITEM_FEATURES_CODE_EN		" Features           [e] "
@@ -846,27 +1208,34 @@
 #define RSC_MENU_ITEM_SYS_REGS_CODE_EN		" System Registers   [R] "
 #define RSC_MENU_ITEM_MEM_CTRL_CODE_EN		" Memory Controller  [M] "
 
-#define RSC_SETTINGS_TITLE_CODE_EN	      " Settings "
-#define RSC_SETTINGS_DAEMON_CODE_EN	      " Daemon gate                    "
-#define RSC_SETTINGS_INTERVAL_CODE_EN	      " Interval(ms)            <    > "
-#define RSC_SETTINGS_SYS_TICK_CODE_EN	      " Sys. Tick(ms)                  "
-#define RSC_SETTINGS_POLL_WAIT_CODE_EN	      " Poll Wait(ms)                  "
-#define RSC_SETTINGS_RING_WAIT_CODE_EN	      " Ring Wait(ms)                  "
-#define RSC_SETTINGS_CHILD_WAIT_CODE_EN       " Child Wait(ms)                 "
-#define RSC_SETTINGS_SLICE_WAIT_CODE_EN       " Slice Wait(ms)                 "
-#define RSC_SETTINGS_RECORDER_CODE_EN	      " Recorder(sec)           <    > "
-#define RSC_SETTINGS_AUTO_CLOCK_CODE_EN       " Auto Clock               <   > "
-#define RSC_SETTINGS_EXPERIMENTAL_CODE_EN     " Experimental             <   > "
-#define RSC_SETTINGS_CPU_HOTPLUG_CODE_EN      " CPU Hot-Plug             [   ] "
-#define RSC_SETTINGS_PCI_ENABLED_CODE_EN      " PCI enablement           [   ] "
-#define RSC_SETTINGS_NMI_REGISTERED_CODE_EN   " NMI registered           <   > "
-#define RSC_SETTINGS_CPUIDLE_REGISTER_CODE_EN " CPU-IDLE driver          <   > "
-#define RSC_SETTINGS_CPUFREQ_REGISTER_CODE_EN " CPU-FREQ driver          <   > "
-#define RSC_SETTINGS_GOVERNOR_CPUFREQ_CODE_EN " Governor driver          <   > "
-#define RSC_SETTINGS_CLOCK_SOURCE_CODE_EN     " Clock Source             <   > "
-#define RSC_SETTINGS_THERMAL_SCOPE_CODE_EN    " Thermal scope           <    > "
-#define RSC_SETTINGS_VOLTAGE_SCOPE_CODE_EN    " Voltage scope           <    > "
-#define RSC_SETTINGS_POWER_SCOPE_CODE_EN      " Power