[Intel 11th to 14th gen] Compute Bus Rate based on BIOS MC PLL

5 files changed, 45 insertions, 30 deletions

diff --git a/corefreq-api.h b/corefreq-api.h
index 66bcd20..4ae64e2 100644
--- a/corefreq-api.h
+++ b/corefreq-api.h
@@ -750,13 +750,13 @@ typedef struct
 		struct {
 			NHM_IMC_CLK_RATIO_STATUS DimmClock;
 			QPI_FREQUENCY		QuickPath;
+			BIOS_MEMCLOCK		BIOS_DDR;
 		};
 	union {
 		struct {
 			MCH_CLKCFG		ClkCfg;
 			SNB_CAPID_A		SNB_Cap;
 			IVB_CAPID_B		IVB_Cap;
-			BIOS_MEMCLOCK		BIOS_DDR;
 		};
 		struct {
 			SNB_EP_CAPID0		SNB_EP_Cap0;
diff --git a/corefreqd.c b/corefreqd.c
index 1242c32..7d30c88 100644
--- a/corefreqd.c
+++ b/corefreqd.c
@@ -5079,22 +5079,9 @@ void RKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 {
 	unsigned int units = 12;
+	unsigned int Bus_Rate = RO(Proc)->Uncore.Bus.BIOS_DDR.MC_PLL_RATIO;
 	unsigned short mc, clock_done;
 
-    if (RO(Proc)->Uncore.Bus.RKL_SA_Pll.UCLK_RATIO > 0) {/* Ring Interconnect */
-	RO(Shm)->Uncore.Bus.Rate = RO(Proc)->Uncore.Bus.RKL_SA_Pll.UCLK_RATIO;
-	RO(Shm)->Uncore.Bus.Rate *= 100;
-	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
-	RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
-    } else {					/* Advertised Bus Speed */
-	RO(Shm)->Uncore.Bus.Rate = 8000;
-	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
-	RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
-    }
-	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
-				* RO(Shm)->Uncore.Bus.Rate)
-				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
-
   for (mc = 0, clock_done = 0;
 	mc < RO(Shm)->Uncore.CtrlCount && !clock_done;
 		mc++)
@@ -5153,6 +5140,8 @@ void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
     {
 	RO(Shm)->Uncore.CtrlSpeed = (266 * units) + ((334 * units) / 501);
 	RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
+
+	Bus_Rate = Bus_Rate * 100U;
     }
     else	/*	Is Memory frequency overclocked ?		*/
     {
@@ -5163,14 +5152,26 @@ void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 		Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 400LLU;
 		Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
 		Freq_Hz = Freq_Hz / 3LLU;
+
+		Bus_Rate = Bus_Rate * 400U;
+		Bus_Rate = Bus_Rate / 3U;
 	} else {
 		Freq_Hz = RO(Proc)->Uncore.Bus.RKL_SA_Pll.QCLK_RATIO;
 		Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 100LLU;
 		Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+		Bus_Rate = Bus_Rate * 100U;
 	}
 	RO(Shm)->Uncore.CtrlSpeed = (unsigned short) Freq_Hz;
 	RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
     }
+	RO(Shm)->Uncore.Bus.Rate = Bus_Rate;
+	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+				* RO(Shm)->Uncore.Bus.Rate)
+				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
+	RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
 	RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
 
 	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.RKL_Cap_A.VT_d;
@@ -5631,22 +5632,9 @@ void ADL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
 void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 {
 	unsigned int units = 12;
+	unsigned int Bus_Rate = RO(Proc)->Uncore.Bus.BIOS_DDR.MC_PLL_RATIO;
 	unsigned short mc, clock_done;
 
-    if (RO(Proc)->Uncore.Bus.ADL_SA_Pll.UCLK_RATIO > 0) {/* Ring Interconnect */
-	RO(Shm)->Uncore.Bus.Rate = RO(Proc)->Uncore.Bus.ADL_SA_Pll.UCLK_RATIO;
-	RO(Shm)->Uncore.Bus.Rate *= 100;
-	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
-	RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
-    } else {					/* Advertised Bus Speed */
-	RO(Shm)->Uncore.Bus.Rate = 8000;
-	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
-	RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
-    }
-	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
-				* RO(Shm)->Uncore.Bus.Rate)
-				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
-
   for (mc = 0, clock_done = 0;
 	mc < RO(Shm)->Uncore.CtrlCount && !clock_done;
 		mc++)
@@ -5705,6 +5693,8 @@ void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
     {
 	RO(Shm)->Uncore.CtrlSpeed = (266 * units) + ((334 * units) / 501);
 	RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
+
+	Bus_Rate = Bus_Rate * 100U;
     }
     else	/*	Is Memory frequency overclocked ?		*/
     {
@@ -5715,14 +5705,26 @@ void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 		Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 400LLU;
 		Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
 		Freq_Hz = Freq_Hz / 3LLU;
+
+		Bus_Rate = Bus_Rate * 400U;
+		Bus_Rate = Bus_Rate / 3U;
 	} else {
 		Freq_Hz = RO(Proc)->Uncore.Bus.ADL_SA_Pll.QCLK_RATIO;
 		Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 100LLU;
 		Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+		Bus_Rate = Bus_Rate * 100U;
 	}
 	RO(Shm)->Uncore.CtrlSpeed = (unsigned short) Freq_Hz;
 	RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
     }
+	RO(Shm)->Uncore.Bus.Rate = Bus_Rate;
+	RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+				* RO(Shm)->Uncore.Bus.Rate)
+				/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+	RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
+	RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
 	RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
 
 	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.ADL_Cap_A.VT_d;
diff --git a/corefreqk.c b/corefreqk.c
index 80e7912..b257b33 100644
--- a/corefreqk.c
+++ b/corefreqk.c
@@ -5102,6 +5102,7 @@ void Query_RKL_IMC(void __iomem *mchmap, unsigned short mc)
     }
     if (mc == 0) {
 	Query_Turbo_TDP_Config(mchmap);
+	BIOS_DDR(mchmap);
 	RKL_SA(mchmap);
     }
 }
@@ -5190,6 +5191,7 @@ void Query_TGL_IMC(void __iomem *mchmap, unsigned short mc)
     }
     if (mc == 0) {
 	Query_Turbo_TDP_Config(mchmap);
+	BIOS_DDR(mchmap);
 	TGL_SA(mchmap);
     }
 EXIT_TGL_IMC:
@@ -5283,6 +5285,7 @@ void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc)
     }
     if (mc == 0) {
 	Query_Turbo_TDP_Config(mchmap);
+	BIOS_DDR(mchmap);
 	ADL_SA(mchmap);
     }
 EXIT_ADL_IMC:
diff --git a/coretypes.h b/coretypes.h
index 9873a2e..5a50b4b 100644
--- a/coretypes.h
+++ b/coretypes.h
@@ -6,7 +6,7 @@
 
 #define COREFREQ_MAJOR	1
 #define COREFREQ_MINOR	95
-#define COREFREQ_REV	3
+#define COREFREQ_REV	4
 
 #if !defined(CORE_COUNT)
 	#define CORE_COUNT	256
diff --git a/intel_reg.h b/intel_reg.h
index 84dc7a1..27a7449 100644
--- a/intel_reg.h
+++ b/intel_reg.h
@@ -3147,6 +3147,16 @@ typedef union
 		PLL_REF100	:  9-8,  /* 0=133,33 MHz , 1=100,00 MHz */
 		ReservedBits2 	: 32-9;
 	};
+	struct {
+		unsigned int
+		MC_PLL_RATIO	:  8-0,  /* Each bin is 133/100MHz	*/
+		MC_PLL_REF	: 12-8,  /* 0=133,33 MHz , 1=100,00 MHz */
+		GEAR		: 14-12, /* 0:QCLK; 1:2xQCLK; 2:4xQCLK	*/
+		ReservedBits 	: 17-14,
+		REQ_VDDQ_TX_VOLT: 27-17,
+		REQ_VDDQ_TX_ICC : 31-27,
+		RUN_BUSY	: 32-31;
+	};
 } BIOS_MEMCLOCK;
 
 typedef union