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authorCyrIng <labs@cyring.fr>2024-02-25 13:09:48 +0100
committerCyrIng <labs@cyring.fr>2024-02-25 13:09:48 +0100
commit96b112b21be0c3ec3aff85f01ce8546cf5ab9977 (patch)
treececc817d9408636e15165bc6a208f0f4a5fd6f33
parent7a7f684320d9efb3af52856fc1744ba1cccacc0e (diff)
[AArch64] Adding other features from ID_AA64ISAR2_EL1
-rw-r--r--aarch64/corefreq-cli-json.c16
-rw-r--r--aarch64/corefreq-cli-rsc-en.h24
-rw-r--r--aarch64/corefreq-cli-rsc-fr.h8
-rw-r--r--aarch64/corefreq-cli-rsc.c16
-rw-r--r--aarch64/corefreq-cli-rsc.h16
-rw-r--r--aarch64/corefreq-cli.c92
-rw-r--r--aarch64/corefreqk.c72
-rw-r--r--aarch64/coretypes.h10
8 files changed, 236 insertions, 18 deletions
diff --git a/aarch64/corefreq-cli-json.c b/aarch64/corefreq-cli-json.c
index 2f3d2e8..d1ea907 100644
--- a/aarch64/corefreq-cli-json.c
+++ b/aarch64/corefreq-cli-json.c
@@ -545,6 +545,22 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PAuth_LR);
json_key(&s, "WFxT");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.WFxT);
+ json_key(&s, "RPRES");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RPRES);
+ json_key(&s, "MOPS");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.MOPS);
+ json_key(&s, "HBC");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.HBC);
+ json_key(&s, "SYSREG128");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SYSREG128);
+ json_key(&s, "SYSINSTR128");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SYSINSTR128);
+ json_key(&s, "PRFMSLC");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.PRFMSLC);
+ json_key(&s, "RPRFM");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.RPRFM);
+ json_key(&s, "CSSC");
+ json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.CSSC);
json_end_object(&s);
}
json_key(&s, "MMFR0");
diff --git a/aarch64/corefreq-cli-rsc-en.h b/aarch64/corefreq-cli-rsc-en.h
index 867fe7b..314b18a 100644
--- a/aarch64/corefreq-cli-rsc-en.h
+++ b/aarch64/corefreq-cli-rsc-en.h
@@ -793,6 +793,9 @@
#define RSC_ISA_JSCVT_COMM_CODE_EN " JavaScript Conversion "
#define RSC_ISA_LRCPC_COMM_CODE_EN " Load-Acquire RCpc instructions "
+#define RSC_ISA_MOPS_COMM_CODE_EN \
+ " Memory Copy and Memory Set instructions "
+
#define RSC_ISA_PACIMP_COMM_CODE_EN \
" Pointer Authentication Code, using Generic key "
@@ -805,12 +808,24 @@
#define RSC_ISA_PAUTH_COMM_CODE_EN " Pointer Authentication "
#define RSC_ISA_PAUTH2_COMM_CODE_EN " Enhanced Pointer Authentication "
#define RSC_ISA_PAUTH_LR_COMM_CODE_EN " Pointer Authentication Link Register "
+#define RSC_ISA_PRFMSLC_COMM_CODE_EN " PRFM instructions support SLC target "
#define RSC_ISA_FRINTTS_COMM_CODE_EN " Floating-point to Integer "
#define RSC_ISA_SPECRES_COMM_CODE_EN " Prediction Invalidation "
#define RSC_ISA_BF16_COMM_CODE_EN " BFloat16 instructions "
#define RSC_ISA_EBF16_COMM_CODE_EN " Extended BFloat16 "
+#define RSC_ISA_CSSC_COMM_CODE_EN " Common Short Sequence Compression "
+#define RSC_ISA_HBC_COMM_CODE_EN " Hinted Conditional Branch "
#define RSC_ISA_I8MM_COMM_CODE_EN " Int8 Matrix Multiplication "
+#define RSC_ISA_RPRES_COMM_CODE_EN \
+ " Reciprocal Estimate & Reciprocal Square Root Estimate "
+
#define RSC_ISA_SB_COMM_CODE_EN " Speculation Barrier "
+#define RSC_ISA_SYSREG128_COMM_CODE_EN \
+ " Instructions to access 128-bit System Registers "
+
+#define RSC_ISA_SYSINSTR128_COMM_CODE_EN \
+ " System instructions that can take 128-bit inputs "
+
#define RSC_ISA_WFxT_COMM_CODE_EN " WFE & WFI instructions with timeout "
#define RSC_ISA_XS_COMM_CODE_EN " XS attribute for memory "
#define RSC_ISA_LS64_COMM_CODE_EN " Atomic 64-byte loads and stores "
@@ -818,6 +833,7 @@
#define RSC_ISA_DPB_COMM_CODE_EN " Data Persistence writeback "
#define RSC_ISA_RAND_COMM_CODE_EN " Read Random Number "
#define RSC_ISA_RDMA_COMM_CODE_EN " Rounding Double Multiply Accumulate "
+#define RSC_ISA_RPRFM_COMM_CODE_EN " RPRFM hint instruction "
#define RSC_ISA_SHA_COMM_CODE_EN " Secure Hash Algorithms extensions "
#define RSC_ISA_SM_COMM_CODE_EN " Chinese cryptography algorithm "
#define RSC_ISA_SIMD_COMM_CODE_EN " Advanced SIMD Extensions "
@@ -1978,19 +1994,26 @@
#define RSC_ISA_LRCPC_CODE " LRCPC [%c]"
#define RSC_ISA_LRCPC2_CODE " LRCPC2 [%c]"
#define RSC_ISA_LRCPC3_CODE " LRCPC3 [%c]"
+#define RSC_ISA_MOPS_CODE " MOPS [%c]"
#define RSC_ISA_PACGA_CODE " PACGA [%c]"
#define RSC_ISA_PACQARMA3_CODE " PACQARMA3 [%c]"
#define RSC_ISA_PACQARMA5_CODE " PACQARMA5 [%c]"
#define RSC_ISA_PAUTH_CODE " PAuth [%c]"
#define RSC_ISA_PAUTH2_CODE " PAuth2 [%c]"
#define RSC_ISA_PAUTH_LR_CODE " PAuth_LR [%c]"
+#define RSC_ISA_PRFMSLC_CODE " PRFMSLC [%c]"
#define RSC_ISA_FRINTTS_CODE " FRINTTS [%c]"
#define RSC_ISA_SPECRES_CODE " SPECRES [%c]"
#define RSC_ISA_SPECRES2_CODE " SPECRES2 [%c]"
#define RSC_ISA_BF16_CODE " BF16 [%c]"
#define RSC_ISA_EBF16_CODE " EBF16 [%c]"
+#define RSC_ISA_CSSC_CODE " CSSC [%c]"
+#define RSC_ISA_HBC_CODE " HBC [%c]"
#define RSC_ISA_I8MM_CODE " I8MM [%c]"
+#define RSC_ISA_RPRES_CODE " RPRES [%c]"
#define RSC_ISA_SB_CODE " SB [%c]"
+#define RSC_ISA_SYSREG128_CODE " SYSREG128 [%c]"
+#define RSC_ISA_SYSINSTR128_CODE " SYSINSTR128 [%c]"
#define RSC_ISA_WFxT_CODE " WFxT [%c]"
#define RSC_ISA_XS_CODE " XS [%c]"
#define RSC_ISA_LS64_CODE " LS64 [%c]"
@@ -2001,6 +2024,7 @@
#define RSC_ISA_DPB2_CODE " DPB2 [%c]"
#define RSC_ISA_RAND_CODE " RAND [%c]"
#define RSC_ISA_RDMA_CODE " RDMA [%c]"
+#define RSC_ISA_RPRFM_CODE " RPRFM [%c]"
#define RSC_ISA_SHA1_CODE " SHA1 [%c]"
#define RSC_ISA_SHA256_CODE " SHA256 [%c]"
#define RSC_ISA_SHA512_CODE " SHA512 [%c]"
diff --git a/aarch64/corefreq-cli-rsc-fr.h b/aarch64/corefreq-cli-rsc-fr.h
index 43206e7..eac18c8 100644
--- a/aarch64/corefreq-cli-rsc-fr.h
+++ b/aarch64/corefreq-cli-rsc-fr.h
@@ -479,18 +479,25 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_ISA_FPACCOMBINE_COMM_CODE_FR RSC_ISA_FPACCOMBINE_COMM_CODE_EN
#define RSC_ISA_JSCVT_COMM_CODE_FR RSC_ISA_JSCVT_COMM_CODE_EN
#define RSC_ISA_LRCPC_COMM_CODE_FR RSC_ISA_LRCPC_COMM_CODE_EN
+#define RSC_ISA_MOPS_COMM_CODE_FR RSC_ISA_MOPS_COMM_CODE_EN
#define RSC_ISA_PACIMP_COMM_CODE_FR RSC_ISA_PACIMP_COMM_CODE_EN
#define RSC_ISA_PACQARMA3_COMM_CODE_FR RSC_ISA_PACQARMA3_COMM_CODE_EN
#define RSC_ISA_PACQARMA5_COMM_CODE_FR RSC_ISA_PACQARMA5_COMM_CODE_EN
#define RSC_ISA_PAUTH_COMM_CODE_FR RSC_ISA_PAUTH_COMM_CODE_EN
#define RSC_ISA_PAUTH2_COMM_CODE_FR RSC_ISA_PAUTH2_COMM_CODE_EN
#define RSC_ISA_PAUTH_LR_COMM_CODE_FR RSC_ISA_PAUTH_LR_COMM_CODE_EN
+#define RSC_ISA_PRFMSLC_COMM_CODE_FR RSC_ISA_PRFMSLC_COMM_CODE_EN
#define RSC_ISA_FRINTTS_COMM_CODE_FR RSC_ISA_FRINTTS_COMM_CODE_EN
#define RSC_ISA_SPECRES_COMM_CODE_FR RSC_ISA_SPECRES_COMM_CODE_EN
#define RSC_ISA_BF16_COMM_CODE_FR RSC_ISA_BF16_COMM_CODE_EN
#define RSC_ISA_EBF16_COMM_CODE_FR RSC_ISA_EBF16_COMM_CODE_EN
+#define RSC_ISA_CSSC_COMM_CODE_FR RSC_ISA_CSSC_COMM_CODE_EN
+#define RSC_ISA_HBC_COMM_CODE_FR RSC_ISA_HBC_COMM_CODE_EN
#define RSC_ISA_I8MM_COMM_CODE_FR RSC_ISA_I8MM_COMM_CODE_EN
+#define RSC_ISA_RPRES_COMM_CODE_FR RSC_ISA_RPRES_COMM_CODE_EN
#define RSC_ISA_SB_COMM_CODE_FR RSC_ISA_SB_COMM_CODE_EN
+#define RSC_ISA_SYSREG128_COMM_CODE_FR RSC_ISA_SYSREG128_COMM_CODE_EN
+#define RSC_ISA_SYSINSTR128_COMM_CODE_FR RSC_ISA_SYSINSTR128_COMM_CODE_EN
#define RSC_ISA_WFxT_COMM_CODE_FR RSC_ISA_WFxT_COMM_CODE_EN
#define RSC_ISA_XS_COMM_CODE_FR RSC_ISA_XS_COMM_CODE_EN
#define RSC_ISA_LS64_COMM_CODE_FR RSC_ISA_LS64_COMM_CODE_EN
@@ -498,6 +505,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_ISA_DPB_COMM_CODE_FR RSC_ISA_DPB_COMM_CODE_EN
#define RSC_ISA_RAND_COMM_CODE_FR RSC_ISA_RAND_COMM_CODE_EN
#define RSC_ISA_RDMA_COMM_CODE_FR RSC_ISA_RDMA_COMM_CODE_EN
+#define RSC_ISA_RPRFM_COMM_CODE_FR RSC_ISA_RPRFM_COMM_CODE_EN
#define RSC_ISA_SHA_COMM_CODE_FR RSC_ISA_SHA_COMM_CODE_EN
#define RSC_ISA_SM_COMM_CODE_FR RSC_ISA_SM_COMM_CODE_EN
#define RSC_ISA_SIMD_COMM_CODE_FR RSC_ISA_SIMD_COMM_CODE_EN
diff --git a/aarch64/corefreq-cli-rsc.c b/aarch64/corefreq-cli-rsc.c
index 350523e..f4886ed 100644
--- a/aarch64/corefreq-cli-rsc.c
+++ b/aarch64/corefreq-cli-rsc.c
@@ -699,6 +699,8 @@ RESOURCE_ST Resource[] = {
LDQ(RSC_ISA_LRCPC2),
LDQ(RSC_ISA_LRCPC3),
LDT(RSC_ISA_LRCPC_COMM),
+ LDQ(RSC_ISA_MOPS),
+ LDT(RSC_ISA_MOPS_COMM),
LDQ(RSC_ISA_PACGA),
LDT(RSC_ISA_PACIMP_COMM),
LDQ(RSC_ISA_PACQARMA3),
@@ -711,6 +713,8 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_PAUTH2_COMM),
LDQ(RSC_ISA_PAUTH_LR),
LDT(RSC_ISA_PAUTH_LR_COMM),
+ LDQ(RSC_ISA_PRFMSLC),
+ LDT(RSC_ISA_PRFMSLC_COMM),
LDQ(RSC_ISA_FRINTTS),
LDT(RSC_ISA_FRINTTS_COMM),
LDQ(RSC_ISA_SPECRES),
@@ -720,10 +724,20 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_BF16_COMM),
LDQ(RSC_ISA_EBF16),
LDT(RSC_ISA_EBF16_COMM),
+ LDQ(RSC_ISA_CSSC),
+ LDT(RSC_ISA_CSSC_COMM),
+ LDQ(RSC_ISA_HBC),
+ LDT(RSC_ISA_HBC_COMM),
LDQ(RSC_ISA_I8MM),
LDT(RSC_ISA_I8MM_COMM),
+ LDQ(RSC_ISA_RPRES),
+ LDT(RSC_ISA_RPRES_COMM),
LDQ(RSC_ISA_SB),
LDT(RSC_ISA_SB_COMM),
+ LDQ(RSC_ISA_SYSREG128),
+ LDT(RSC_ISA_SYSREG128_COMM),
+ LDQ(RSC_ISA_SYSINSTR128),
+ LDT(RSC_ISA_SYSINSTR128_COMM),
LDQ(RSC_ISA_WFxT),
LDT(RSC_ISA_WFxT_COMM),
LDQ(RSC_ISA_XS),
@@ -741,6 +755,8 @@ RESOURCE_ST Resource[] = {
LDT(RSC_ISA_RAND_COMM),
LDQ(RSC_ISA_RDMA),
LDT(RSC_ISA_RDMA_COMM),
+ LDQ(RSC_ISA_RPRFM),
+ LDT(RSC_ISA_RPRFM_COMM),
LDQ(RSC_ISA_SHA1),
LDQ(RSC_ISA_SHA256),
LDQ(RSC_ISA_SHA512),
diff --git a/aarch64/corefreq-cli-rsc.h b/aarch64/corefreq-cli-rsc.h
index 8b27220..72bbb16 100644
--- a/aarch64/corefreq-cli-rsc.h
+++ b/aarch64/corefreq-cli-rsc.h
@@ -522,6 +522,8 @@ enum {
RSC_ISA_LRCPC2,
RSC_ISA_LRCPC3,
RSC_ISA_LRCPC_COMM,
+ RSC_ISA_MOPS,
+ RSC_ISA_MOPS_COMM,
RSC_ISA_PACGA,
RSC_ISA_PACIMP_COMM,
RSC_ISA_PACQARMA3,
@@ -534,6 +536,8 @@ enum {
RSC_ISA_PAUTH2_COMM,
RSC_ISA_PAUTH_LR,
RSC_ISA_PAUTH_LR_COMM,
+ RSC_ISA_PRFMSLC,
+ RSC_ISA_PRFMSLC_COMM,
RSC_ISA_FRINTTS,
RSC_ISA_FRINTTS_COMM,
RSC_ISA_SPECRES,
@@ -543,10 +547,20 @@ enum {
RSC_ISA_BF16_COMM,
RSC_ISA_EBF16,
RSC_ISA_EBF16_COMM,
+ RSC_ISA_CSSC,
+ RSC_ISA_CSSC_COMM,
+ RSC_ISA_HBC,
+ RSC_ISA_HBC_COMM,
RSC_ISA_I8MM,
RSC_ISA_I8MM_COMM,
+ RSC_ISA_RPRES,
+ RSC_ISA_RPRES_COMM,
RSC_ISA_SB,
RSC_ISA_SB_COMM,
+ RSC_ISA_SYSREG128,
+ RSC_ISA_SYSREG128_COMM,
+ RSC_ISA_SYSINSTR128,
+ RSC_ISA_SYSINSTR128_COMM,
RSC_ISA_WFxT,
RSC_ISA_WFxT_COMM,
RSC_ISA_XS,
@@ -564,6 +578,8 @@ enum {
RSC_ISA_RAND_COMM,
RSC_ISA_RDMA,
RSC_ISA_RDMA_COMM,
+ RSC_ISA_RPRFM,
+ RSC_ISA_RPRFM_COMM,
RSC_ISA_SHA1,
RSC_ISA_SHA256,
RSC_ISA_SHA512,
diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c
index dc688e1..ca26d10 100644
--- a/aarch64/corefreq-cli.c
+++ b/aarch64/corefreq-cli.c
@@ -1507,6 +1507,13 @@ REASON_CODE SysInfoISA( Window *win,
/* Row Mark */
{
NULL,
+ RSC(ISA_CSSC).CODE(), RSC(ISA_CSSC_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.CSSC },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.CSSC },
+ },
+ {
+ NULL,
RSC(ISA_DGH).CODE(), RSC(ISA_DGH_COMM).CODE(),
{ 0, RO(Shm)->Proc.Features.DGH },
(unsigned short[])
@@ -1526,6 +1533,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.DPB },
},
+/* Row Mark */
{
NULL,
RSC(ISA_DPB2).CODE(), RSC(ISA_DPB_COMM).CODE(),
@@ -1533,7 +1541,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.DPB2 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_EBF16).CODE(), RSC(ISA_EBF16_COMM).CODE(),
@@ -1555,6 +1562,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.FCMA },
},
+/* Row Mark */
{
NULL,
RSC(ISA_FHM).CODE(), RSC(ISA_FHM_COMM).CODE(),
@@ -1562,7 +1570,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.FHM },
},
-/* Row Mark */
{
NULL,
RSC(ISA_FlagM).CODE(), RSC(ISA_FlagM_COMM).CODE(),
@@ -1584,6 +1591,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.FP },
},
+/* Row Mark */
{
NULL,
RSC(ISA_FPAC).CODE(), RSC(ISA_FPAC_COMM).CODE(),
@@ -1591,7 +1599,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.FPAC },
},
-/* Row Mark */
{
NULL,
RSC(ISA_FPACCOMBINE).CODE(), RSC(ISA_FPACCOMBINE_COMM).CODE(),
@@ -1608,6 +1615,14 @@ REASON_CODE SysInfoISA( Window *win,
},
{
NULL,
+ RSC(ISA_HBC).CODE(), RSC(ISA_HBC_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.HBC },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.HBC },
+ },
+/* Row Mark */
+ {
+ NULL,
RSC(ISA_I8MM).CODE(), RSC(ISA_I8MM_COMM).CODE(),
{ 0, RO(Shm)->Proc.Features.I8MM },
(unsigned short[])
@@ -1620,7 +1635,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.JSCVT },
},
-/* Row Mark */
{
NULL,
RSC(ISA_LRCPC).CODE(), RSC(ISA_LRCPC_COMM).CODE(),
@@ -1635,6 +1649,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.LRCPC2 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_LRCPC3).CODE(), RSC(ISA_LRCPC_COMM).CODE(),
@@ -1649,7 +1664,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.LS64 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_LS64_V).CODE(), RSC(ISA_LS64_COMM).CODE(),
@@ -1664,6 +1678,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.LS64_ACCDATA },
},
+/* Row Mark */
{
NULL,
RSC(ISA_LSE).CODE(), RSC(ISA_LSE_COMM).CODE(),
@@ -1678,7 +1693,13 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.LSE128 },
},
-/* Row Mark */
+ {
+ NULL,
+ RSC(ISA_MOPS).CODE(), RSC(ISA_MOPS_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.MOPS },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.MOPS },
+ },
{
NULL,
RSC(ISA_PACGA).CODE(), RSC(ISA_PACIMP_COMM).CODE(),
@@ -1686,6 +1707,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.PACIMP },
},
+/* Row Mark */
{
NULL,
RSC(ISA_PACQARMA3).CODE(), RSC(ISA_PACQARMA3_COMM).CODE(),
@@ -1707,7 +1729,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.PAuth },
},
-/* Row Mark */
{
NULL,
RSC(ISA_PAUTH2).CODE(), RSC(ISA_PAUTH2_COMM).CODE(),
@@ -1715,6 +1736,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.PAuth2 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_PAUTH_LR).CODE(), RSC(ISA_PAUTH_LR_COMM).CODE(),
@@ -1724,6 +1746,13 @@ REASON_CODE SysInfoISA( Window *win,
},
{
NULL,
+ RSC(ISA_PRFMSLC).CODE(), RSC(ISA_PRFMSLC_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.PRFMSLC },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.PRFMSLC },
+ },
+ {
+ NULL,
RSC(ISA_PMULL).CODE(), RSC(ISA_AES_COMM).CODE(),
{ 0, RO(Shm)->Proc.Features.PMULL },
(unsigned short[])
@@ -1746,11 +1775,26 @@ REASON_CODE SysInfoISA( Window *win,
},
{
NULL,
+ RSC(ISA_RPRES).CODE(), RSC(ISA_RPRES_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.RPRES },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.RPRES },
+ },
+ {
+ NULL,
+ RSC(ISA_RPRFM).CODE(), RSC(ISA_RPRFM_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.RPRFM },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.RPRFM },
+ },
+ {
+ NULL,
RSC(ISA_SB).CODE(), RSC(ISA_SB_COMM).CODE(),
{ 0, RO(Shm)->Proc.Features.SB },
(unsigned short[])
{ RO(Shm)->Proc.Features.SB },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SHA1).CODE(), RSC(ISA_SHA_COMM).CODE(),
@@ -1765,7 +1809,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SHA256 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SHA512).CODE(), RSC(ISA_SHA_COMM).CODE(),
@@ -1780,6 +1823,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SHA3 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SM3).CODE(), RSC(ISA_SM_COMM).CODE(),
@@ -1794,7 +1838,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SM4 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SME).CODE(), RSC(ISA_SME_COMM).CODE(),
@@ -1809,6 +1852,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME2 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SME2p1).CODE(), RSC(ISA_SME_COMM).CODE(),
@@ -1823,7 +1867,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_FA64 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SME_LUTv2).CODE(), NULL,
@@ -1838,6 +1881,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_I16I64 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SME_F64F64).CODE(), NULL,
@@ -1852,7 +1896,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_I16I32 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SME_B16B16).CODE(), NULL,
@@ -1867,6 +1910,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_F16F16 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SME_F8F16).CODE(), NULL,
@@ -1881,7 +1925,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_F8F32 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SME_I8I32).CODE(), NULL,
@@ -1896,6 +1939,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_F16F32 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SME_B16F32).CODE(), NULL,
@@ -1910,7 +1954,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_BI32I32 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SME_F32F32).CODE(), NULL,
@@ -1925,6 +1968,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_SF8FMA },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SME_SF8DP4).CODE(), NULL,
@@ -1939,7 +1983,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SME_SF8DP2 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SPECRES).CODE(), RSC(ISA_SPECRES_COMM).CODE(),
@@ -1954,6 +1997,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SPECRES2 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SVE).CODE(), RSC(ISA_SVE_COMM).CODE(),
@@ -1968,7 +2012,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE2 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SVE_F64MM).CODE(), NULL,
@@ -1983,6 +2026,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE_F32MM },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SVE_I8MM).CODE(), NULL,
@@ -1997,7 +2041,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE_SM4 },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SVE_SHA3).CODE(), NULL,
@@ -2012,6 +2055,7 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE_BF16 },
},
+/* Row Mark */
{
NULL,
RSC(ISA_SVE_EBF16).CODE(), NULL,
@@ -2026,7 +2070,6 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE_BitPerm },
},
-/* Row Mark */
{
NULL,
RSC(ISA_SVE_AES).CODE(), NULL,
@@ -2041,6 +2084,21 @@ REASON_CODE SysInfoISA( Window *win,
(unsigned short[])
{ RO(Shm)->Proc.Features.SVE_PMULL128 },
},
+/* Row Mark */
+ {
+ NULL,
+ RSC(ISA_SYSREG128).CODE(), RSC(ISA_SYSREG128_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.SYSREG128 },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.SYSREG128 },
+ },
+ {
+ NULL,
+ RSC(ISA_SYSINSTR128).CODE(), RSC(ISA_SYSINSTR128_COMM).CODE(),
+ { 0, RO(Shm)->Proc.Features.SYSINSTR128 },
+ (unsigned short[])
+ { RO(Shm)->Proc.Features.SYSINSTR128 },
+ },
{
NULL,
RSC(ISA_WFxT).CODE(), RSC(ISA_WFxT_COMM).CODE(),
diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
index 10a3971..0ad5ae9 100644
--- a/aarch64/corefreqk.c
+++ b/aarch64/corefreqk.c
@@ -958,6 +958,78 @@ static void Query_Features(void *pArg)
iArg->Features->WFxT = 0;
break;
}
+ switch (isar2.RPRES) {
+ case 0b0010:
+ iArg->Features->RPRES = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->RPRES = 0;
+ break;
+ }
+ switch (isar2.MOPS) {
+ case 0b0010:
+ iArg->Features->MOPS = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->MOPS = 0;
+ break;
+ }
+ switch (isar2.BC) {
+ case 0b0010:
+ iArg->Features->HBC = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->HBC = 0;
+ break;
+ }
+ switch (isar2.SYSREG_128) {
+ case 0b0010:
+ iArg->Features->SYSREG128 = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->SYSREG128 = 0;
+ break;
+ }
+ switch (isar2.SYSINSTR_128) {
+ case 0b0010:
+ iArg->Features->SYSINSTR128 = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->SYSINSTR128 = 0;
+ break;
+ }
+ switch (isar2.PRFMSLC) {
+ case 0b0010:
+ iArg->Features->PRFMSLC = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->PRFMSLC = 0;
+ break;
+ }
+ switch (isar2.RPRFM) {
+ case 0b0010:
+ iArg->Features->RPRFM = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->RPRFM = 0;
+ break;
+ }
+ switch (isar2.CSSC) {
+ case 0b0010:
+ iArg->Features->CSSC = 1;
+ break;
+ case 0b0000:
+ default:
+ iArg->Features->CSSC = 0;
+ break;
+ }
switch (mmfr0.ECV) {
case 0b0010:
case 0b0001:
diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h
index d52cefd..c473845 100644
--- a/aarch64/coretypes.h
+++ b/aarch64/coretypes.h
@@ -899,7 +899,15 @@ typedef struct /* BSP features. */
Bit64 PAuth_LR : 1-0,
WFxT : 2-1,
- _Unused1_ : 64-2;
+ RPRES : 3-2,
+ MOPS : 4-3,
+ HBC : 5-4,
+ SYSREG128 : 6-5,
+ SYSINSTR128 : 7-6,
+ PRFMSLC : 8-7,
+ RPRFM : 9-8,
+ CSSC : 10-9,
+ _Unused1_ : 64-10;
Bit64 InvariantTSC : 8-0,
HyperThreading : 9-8,