diff options
| author | CyrIng <labs@cyring.fr> | 2024-08-12 00:35:24 +0200 |
|---|---|---|
| committer | CyrIng <labs@cyring.fr> | 2024-08-12 00:35:24 +0200 |
| commit | 8ca842b164f196d6205a401d469c3274315227e0 (patch) | |
| tree | 012443de74d107bf78e4660f351ab8bfec311418 | |
| parent | bd68f0407c50a17e4787a7d3ee1a099aea924213 (diff) | |
[Intel][WDT] Based on C620 Series PCH datasheet, probe TCO devices1.98.2
* C620 Series Chipset Production SKUs (`0xa1a3`)
* C620 Series Chipset Super SKUs (`0xa223`)
| -rw-r--r-- | x86_64/corefreq-api.h | 3 | ||||
| -rw-r--r-- | x86_64/corefreqk.c | 8 |
2 files changed, 11 insertions, 0 deletions
diff --git a/x86_64/corefreq-api.h b/x86_64/corefreq-api.h index 7e19e39..8b59c97 100644 --- a/x86_64/corefreq-api.h +++ b/x86_64/corefreq-api.h @@ -1384,6 +1384,9 @@ typedef struct #define DID_INTEL_SKYLAKE_H_IMC_HAQ 0x1910 /* Source: Intel Xeon Processor E3-1200 v5 Product Family */ #define DID_INTEL_SKYLAKE_DT_IMC_HA 0x1918 +/* Source: Intel C620 Series Chipset Platform Controller Hub Datasheet */ +#define DID_INTEL_C620_PCH_SMBUS 0xa1a3 +#define DID_INTEL_C620_SUPER_SMBUS 0xa223 /* Source:7th Generation Intel Processor for S-Platforms & Core X-Series Vol2*/ #define DID_INTEL_KABYLAKE_H_IMC_HAD 0x5900 #define DID_INTEL_KABYLAKE_U_IMC_HA 0x5904 diff --git a/x86_64/corefreqk.c b/x86_64/corefreqk.c index 241e67d..6ae9cdd 100644 --- a/x86_64/corefreqk.c +++ b/x86_64/corefreqk.c @@ -10382,6 +10382,14 @@ static void Intel_Watchdog(CORE_RO *Core) .driver_data = (kernel_ulong_t) TCOBASE }, { + PCI_VDEVICE(INTEL, DID_INTEL_C620_PCH_SMBUS), + .driver_data = (kernel_ulong_t) TCOBASE + }, + { + PCI_VDEVICE(INTEL, DID_INTEL_C620_SUPER_SMBUS), + .driver_data = (kernel_ulong_t) TCOBASE + }, + { PCI_VDEVICE(INTEL, DID_INTEL_KBL_PCH_H_SMBUS), .driver_data = (kernel_ulong_t) TCOBASE }, |