doc/man7/EVP_ASYM_CIPHER-SM2.pod


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=pod

=head1 NAME

EVP_ASYM_CIPHER-SM2
- SM2 Asymmetric Cipher algorithm support

=head1 DESCRIPTION

Asymmetric Cipher support for the B<SM2> key type.

=head2 SM2 Asymmetric Cipher parameters

=over 4

=item "digest" (B<OSSL_ASYM_CIPHER_PARAM_DIGEST>) <UTF8 string>

=item "digest-props" (B<OSSL_ASYM_CIPHER_PARAM_DIGEST_PROPS>) <UTF8 string>

See L<provider-asym_cipher(7)/Asymmetric Cipher Parameters>.

=back

=head1 SEE ALSO

L<EVP_PKEY-SM2(7)>,
L<EVP_PKEY(3)>,
L<provider-asym_cipher(7)>,
L<provider-keymgmt(7)>,
L<OSSL_PROVIDER-default(7)>

=head1 COPYRIGHT

Copyright 2020 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License").  You may not use
this file except in compliance with the License.  You can obtain a copy
in the file LICENSE in the source distribution or at
L<https://www.openssl.org/source/license.html>.

=cut
/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
 *    Copyright 2016 Microsemi Corporation
 *    Copyright 2014-2015 PMC-Sierra, Inc.
 *    Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
 *
 */
#ifndef HPSA_CMD_H
#define HPSA_CMD_H

/* general boundary defintions */
#define SENSEINFOBYTES          32 /* may vary between hbas */
#define SG_ENTRIES_IN_CMD	32 /* Max SG entries excluding chain blocks */
#define HPSA_SG_CHAIN		0x80000000
#define HPSA_SG_LAST		0x40000000
#define MAXREPLYQS              256

/* Command Status value */
#define CMD_SUCCESS             0x0000
#define CMD_TARGET_STATUS       0x0001
#define CMD_DATA_UNDERRUN       0x0002
#define CMD_DATA_OVERRUN        0x0003
#define CMD_INVALID             0x0004
#define CMD_PROTOCOL_ERR        0x0005
#define CMD_HARDWARE_ERR        0x0006
#define CMD_CONNECTION_LOST     0x0007
#define CMD_ABORTED             0x0008
#define CMD_ABORT_FAILED        0x0009
#define CMD_UNSOLICITED_ABORT   0x000A
#define CMD_TIMEOUT             0x000B
#define CMD_UNABORTABLE		0x000C
#define CMD_TMF_STATUS		0x000D
#define CMD_IOACCEL_DISABLED	0x000E
#define CMD_CTLR_LOCKUP		0xffff
/* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
 * it is a value defined by the driver that commands can be marked
 * with when a controller lockup has been detected by the driver
 */

/* TMF function status values */
#define CISS_TMF_COMPLETE	0x00
#define CISS_TMF_INVALID_FRAME	0x02
#define CISS_TMF_NOT_SUPPORTED	0x04
#define CISS_TMF_FAILED		0x05
#define CISS_TMF_SUCCESS	0x08
#define CISS_TMF_WRONG_LUN	0x09
#define CISS_TMF_OVERLAPPED_TAG 0x0a

/* Unit Attentions ASC's as defined for the MSA2012sa */
#define POWER_OR_RESET			0x29
#define STATE_CHANGED			0x2a
#define UNIT_ATTENTION_CLEARED		0x2f
#define LUN_FAILED			0x3e
#define REPORT_LUNS_CHANGED		0x3f

/* Unit Attentions ASCQ's as defined for the MSA2012sa */

	/* These ASCQ's defined for ASC = POWER_OR_RESET */
#define POWER_ON_RESET			0x00
#define POWER_ON_REBOOT			0x01
#define SCSI_BUS_RESET			0x02
#define MSA_TARGET_RESET		0x03
#define CONTROLLER_FAILOVER		0x04
#define TRANSCEIVER_SE			0x05
#define TRANSCEIVER_LVD			0x06

	/* These ASCQ's defined for ASC = STATE_CHANGED */
#define RESERVATION_PREEMPTED		0x03
#define ASYM_ACCESS_CHANGED		0x06
#define LUN_CAPACITY_CHANGED		0x09

/* transfer direction */
#define XFER_NONE               0x00
#define XFER_WRITE              0x01
#define XFER_READ               0x02
#define XFER_RSVD               0x03

/* task attribute */
#define ATTR_UNTAGGED           0x00
#define ATTR_SIMPLE             0x04
#define ATTR_HEADOFQUEUE        0x05
#define ATTR_ORDERED            0x06
#define ATTR_ACA                0x07

/* cdb type */
#define TYPE_CMD		0x00
#define TYPE_MSG		0x01
#define TYPE_IOACCEL2_CMD	0x81 /* 0x81 is not used by hardware */

/* Message Types  */
#define HPSA_TASK_MANAGEMENT    0x00
#define HPSA_RESET              0x01
#define HPSA_SCAN               0x02
#define HPSA_NOOP               0x03

#define HPSA_CTLR_RESET_TYPE    0x00
#define HPSA_BUS_RESET_TYPE     0x01
#define HPSA_TARGET_RESET_TYPE  0x03
#define HPSA_LUN_RESET_TYPE     0x04
#define HPSA_NEXUS_RESET_TYPE   0x05

/* Task Management Functions */
#define HPSA_TMF_ABORT_TASK     0x00
#define HPSA_TMF_ABORT_TASK_SET 0x01
#define HPSA_TMF_CLEAR_ACA      0x02
#define HPSA_TMF_CLEAR_TASK_SET 0x03
#define HPSA_TMF_QUERY_TASK     0x04
#define HPSA_TMF_QUERY_TASK_SET 0x05
#define HPSA_TMF_QUERY_ASYNCEVENT 0x06


/* config space register offsets */
#define CFG_VENDORID            0x00
#define CFG_DEVICEID            0x02
#define CFG_I2OBAR              0x10
#define CFG_MEM1BAR             0x14

/* i2o space register offsets */
#define I2O_IBDB_SET            0x20
#define I2O_IBDB_CLEAR          0x70
#define I2O_INT_STATUS          0x30
#define I2O_INT_MASK            0x34
#define I2O_IBPOST_Q            0x40
#define I2O_OBPOST_Q            0x44
#define I2O_DMA1_CFG		0x214

/* Configuration Table */
#define CFGTBL_ChangeReq        0x00000001l
#define CFGTBL_AccCmds          0x00000001l
#define DOORBELL_CTLR_RESET	0x00000004l
#define DOORBELL_CTLR_RESET2	0x00000020l
#define DOORBELL_CLEAR_EVENTS	0x00000040l
#define DOORBELL_GENERATE_CHKPT	0x00000080l

#define CFGTBL_Trans_Simple     0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l
#define CFGTBL_Trans_io_accel1	0x00000080l
#define CFGTBL_Trans_io_accel2	0x00000100l
#define CFGTBL_Trans_use_short_tags 0x20000000l
#define CFGTBL_Trans_enable_directed_msix (1 << 30)

#define CFGTBL_BusType_Ultra2   0x00000001l
#define CFGTBL_BusType_Ultra3   0x00000002l
#define CFGTBL_BusType_Fibre1G  0x00000100l
#define CFGTBL_BusType_Fibre2G  0x00000200l

/* VPD Inquiry types */
#define HPSA_INQUIRY_FAILED		0x02
#define HPSA_VPD_SUPPORTED_PAGES        0x00
#define HPSA_VPD_LV_DEVICE_ID           0x83
#define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
#define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
#define HPSA_VPD_LV_STATUS		0xC3
#define HPSA_VPD_HEADER_SZ              4

/* Logical volume states */
#define HPSA_VPD_LV_STATUS_UNSUPPORTED			0xff
#define HPSA_LV_OK                                      0x0
#define HPSA_LV_FAILED					0x01
#define HPSA_LV_NOT_AVAILABLE				0x0b
#define HPSA_LV_UNDERGOING_ERASE			0x0F
#define HPSA_LV_UNDERGOING_RPI				0x12
#define HPSA_LV_PENDING_RPI				0x13
#define HPSA_LV_ENCRYPTED_NO_KEY			0x14
#define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER	0x15
#define HPSA_LV_UNDERGOING_ENCRYPTION			0x16
#define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING		0x17
#define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER	0x18
#define HPSA_LV_PENDING_ENCRYPTION			0x19
#define HPSA_LV_PENDING_ENCRYPTION_REKEYING		0x1A

struct vals32 {
	u32   lower;
	u32   upper;
};

union u64bit {
	struct vals32 val32;
	u64 val;
};

/* FIXME this is a per controller value (barf!) */
#define HPSA_MAX_LUN 1024
#define HPSA_MAX_PHYS_LUN 1024
#define MAX_EXT_TARGETS 32
#define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
	MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */

/* SCSI-3 Commands */
#pragma pack(1)

#define HPSA_INQUIRY 0x12
struct InquiryData {
	u8 data_byte[36];
};

#define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
#define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
#define HPSA_REPORT_PHYS_EXTENDED 0x02
#define HPSA_CISS_READ	0xc0	/* CISS Read */
#define HPSA_GET_RAID_MAP 0xc8	/* CISS Get RAID Layout Map */

#define RAID_MAP_MAX_ENTRIES   256

struct raid_map_disk_data {
	u32   ioaccel_handle;         /**< Handle to access this disk via the
					*  I/O accelerator */
	u8    xor_mult[2];            /**< XOR multipliers for this position,
					*  valid for data disks only */
	u8    reserved[2];
};

struct raid_map_data {
	__le32   structure_size;	/* Size of entire structure in bytes */
	__le32   volume_blk_size;	/* bytes / block in the volume */
	__le64   volume_blk_cnt;	/* logical blocks on the volume */
	u8    phys_blk_shift;		/* Shift factor to convert between
					 * units of logical blocks and physical
					 * disk blocks */
	u8    parity_rotation_shift;	/* Shift factor to convert between units
					 * of logical stripes and physical
					 * stripes */
	__le16   strip_size;		/* blocks used on each disk / stripe */
	__le64   disk_starting_blk;	/* First disk block used in volume */
	__le64   disk_blk_cnt;		/* disk blocks used by volume / disk */
	__le16   data_disks_per_row;	/* data disk entries / row in the map */
	__le16   metadata_disks_per_row;/* mirror/parity disk entries / row
					 * in the map */
	__le16   row_cnt;		/* rows in each layout map */
	__le16   layout_map_count;	/* layout maps (1 map per mirror/parity
					 * group) */
	__le16   flags;			/* Bit 0 set if encryption enabled */
#define RAID_MAP_FLAG_ENCRYPT_ON  0x01
	__le16   dekindex;		/* Data encryption key index. */
	u8    reserved[16];
	struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
};

struct ReportLUNdata {
	u8 LUNListLength[4];
	u8 extended_response_flag;
	u8 reserved[3];
	u8 LUN[HPSA_MAX_LUN][8];
};

struct ext_report_lun_entry {
	u8 lunid[8];
#define MASKED_DEVICE(x) ((x)[3] & 0xC0)
#define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
#define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
#define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
			GET_BMIC_LEVEL_TWO_TARGET((lunid)))
	u8 wwid[8];
	u8 device_type;
	u8 device_flags;
	u8 lun_count; /* multi-lun device, how many luns */
	u8 redundant_paths;
	u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
};

struct ReportExtendedLUNdata {
	u8 LUNListLength[4];
	u8 extended_response_flag;
	u8 reserved[3];
	struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
};

struct SenseSubsystem_info {
	u8 reserved[36];
	u8 portname[8];
	u8 reserved1[1108];
};

/* BMIC commands */
#define BMIC_READ 0x26
#define BMIC_WRITE 0x27
#define BMIC_CACHE_FLUSH 0xc2
#define HPSA_CACHE_FLUSH 0x01	/* C2 was already being used by HPSA */
#define BMIC_FLASH_FIRMWARE 0xF7
#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
#define BMIC_IDENTIFY_CONTROLLER 0x11
#define BMIC_SET_DIAG_OPTIONS 0xF4
#define BMIC_SENSE_DIAG_OPTIONS 0xF5
#define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
#define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65

/* Command List Structure */
union SCSI3Addr {
	struct {
		u8 Dev;
		u8 Bus:6;
		u8 Mode:2;        /* b00 */
	} PeripDev;
	struct {
		u8 DevLSB;
		u8 DevMSB:6;
		u8 Mode:2;        /* b01 */
	} LogDev;
	struct {
		u8 Dev:5;
		u8 Bus:3;
		u8 Targ:6;
		u8 Mode:2;        /* b10 */
	} LogUnit;
};

struct PhysDevAddr {
	u32             TargetId:24;
	u32             Bus:6;
	u32             Mode:2;
	/* 2 level target device addr */
	union SCSI3Addr  Target[2];
};

struct LogDevAddr {
	u32            VolId:30;
	u32            Mode:2;