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-rw-r--r--crypto/arm_arch.h3
-rw-r--r--crypto/armcap.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h
index b76981f48b..da999b5f6d 100644
--- a/crypto/arm_arch.h
+++ b/crypto/arm_arch.h
@@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define ARM_CPU_IMP_ARM 0x41
# define HISI_CPU_IMP 0x48
# define ARM_CPU_IMP_APPLE 0x61
+# define ARM_CPU_IMP_MICROSOFT 0x6D
# define ARM_CPU_PART_CORTEX_A72 0xD08
# define ARM_CPU_PART_N1 0xD0C
@@ -124,6 +125,8 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
+# define MICROSOFT_CPU_PART_COBALT_100 0xD49
+
# define MIDR_PARTNUM_SHIFT 4
# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM(midr) \
diff --git a/crypto/armcap.c b/crypto/armcap.c
index adb8b6a188..bbb9f454fc 100644
--- a/crypto/armcap.c
+++ b/crypto/armcap.c
@@ -418,6 +418,7 @@ void OPENSSL_cpuid_setup(void)
}
if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) ||
+ MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) ||
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) &&
(OPENSSL_armcap_P & ARMV8_SHA3))
OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;