diff options
| author | Tom Cosgrove <tom.cosgrove@arm.com> | 2024-02-21 09:11:20 +0000 |
|---|---|---|
| committer | Tomas Mraz <tomas@openssl.org> | 2024-02-22 16:07:02 +0100 |
| commit | 11adf9a75d6b34723d1a20a0da4e4100ea6ca593 (patch) | |
| tree | 4c3c70e72aa596228427bc1e87ceba1c8e9a3e34 | |
| parent | 1afb326da4b3a781dc0d7cd91262d81126783b07 (diff) | |
Apply the AES-GCM unroll8 optimisation to Microsoft Azure Cobalt 100
Performance improvements range from 18% to 32%.
Change-Id: Ifb89eeac3c0625a582a25ff07cf7f9c9ec8f5ba6
Reviewed-by: Hugo Landau <hlandau@openssl.org>
Reviewed-by: Neil Horman <nhorman@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/23651)
| -rw-r--r-- | crypto/arm_arch.h | 3 | ||||
| -rw-r--r-- | crypto/armcap.c | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index b76981f48b..da999b5f6d 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define ARM_CPU_IMP_ARM 0x41 # define HISI_CPU_IMP 0x48 # define ARM_CPU_IMP_APPLE 0x61 +# define ARM_CPU_IMP_MICROSOFT 0x6D # define ARM_CPU_PART_CORTEX_A72 0xD08 # define ARM_CPU_PART_N1 0xD0C @@ -124,6 +125,8 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 # define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 +# define MICROSOFT_CPU_PART_COBALT_100 0xD49 + # define MIDR_PARTNUM_SHIFT 4 # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT) # define MIDR_PARTNUM(midr) \ diff --git a/crypto/armcap.c b/crypto/armcap.c index adb8b6a188..bbb9f454fc 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -418,6 +418,7 @@ void OPENSSL_cpuid_setup(void) } if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; |