diff options
| author | sdlyyxy <sdlyyxy@icloud.com> | 2023-07-07 19:26:10 +0800 |
|---|---|---|
| committer | Pauli <pauli@openssl.org> | 2023-07-21 10:19:19 +1000 |
| commit | f6484de23df5f04e1f9fa8418e942c45c1a65578 (patch) | |
| tree | 487e136cf7d68e78ae7f14ba2b442300001570d4 /crypto | |
| parent | 0c85bcbaeabe3a695831bec44ab87964725a51a6 (diff) | |
Enable ARMv8.2 accelerated SHA3 on compatible Apple CPUs
The hardware-assisted ARMv8.2 implementation is already in keccak1600-armv8.pl.
It is not called because the author mentioned that it's not actually obvious
that it will provide performance improvements. The test on Apple M1 Firestorm
shows that the ARMv8.2 implementation could improve about 36% for large blocks.
So let's enable ARMv8.2 accelerated SHA3 on Apple CPU family.
Fixes #21380
Reviewed-by: Tom Cosgrove <tom.cosgrove@arm.com>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21398)
Diffstat (limited to 'crypto')
| -rw-r--r-- | crypto/arm_arch.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index cc5cc5ba49..b1bb65c7dc 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -98,6 +98,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define ARM_CPU_IMP_ARM 0x41 # define HISI_CPU_IMP 0x48 +# define ARM_CPU_IMP_APPLE 0x61 # define ARM_CPU_PART_CORTEX_A72 0xD08 # define ARM_CPU_PART_N1 0xD0C @@ -106,6 +107,19 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define HISI_CPU_PART_KP920 0xD01 # define ARM_CPU_PART_V2 0xD4F +# define APPLE_CPU_PART_M1_ICESTORM 0x022 +# define APPLE_CPU_PART_M1_FIRESTORM 0x023 +# define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 +# define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 +# define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 +# define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 +# define APPLE_CPU_PART_M2_BLIZZARD 0x032 +# define APPLE_CPU_PART_M2_AVALANCHE 0x033 +# define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 +# define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 +# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 +# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 + # define MIDR_PARTNUM_SHIFT 4 # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT) # define MIDR_PARTNUM(midr) \ |