diff options
| author | Jiangning Liu <jiangning.liu@amperecomputing.com> | 2024-03-21 16:52:28 -0700 |
|---|---|---|
| committer | Tomas Mraz <tomas@openssl.org> | 2024-04-08 11:54:29 +0200 |
| commit | e7f1afe4f7e799394684ce86bd98f2445031eb7f (patch) | |
| tree | 31bce6208bc2e86d6a408fa0da73c9293aa0eef3 /crypto | |
| parent | 0d2a5f600c7b6bef6fa6cf720204876560a6194b (diff) | |
Enable SHA3 unrolling and EOR3 optimization for Ampere
Reviewed-by: Tom Cosgrove <tom.cosgrove@arm.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/23929)
Diffstat (limited to 'crypto')
| -rw-r--r-- | crypto/arm_arch.h | 1 | ||||
| -rw-r--r-- | crypto/armcap.c | 6 |
2 files changed, 5 insertions, 2 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index da999b5f6d..09473dd0b8 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -104,6 +104,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; # define HISI_CPU_IMP 0x48 # define ARM_CPU_IMP_APPLE 0x61 # define ARM_CPU_IMP_MICROSOFT 0x6D +# define ARM_CPU_IMP_AMPERE 0xC0 # define ARM_CPU_PART_CORTEX_A72 0xD08 # define ARM_CPU_PART_N1 0xD0C diff --git a/crypto/armcap.c b/crypto/armcap.c index bbb9f454fc..afd3e9083e 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -419,11 +419,13 @@ void OPENSSL_cpuid_setup(void) if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) || - MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) || + MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || - MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) || + MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL12_EOR3; if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) || |