diff options
| author | Andrey Matyukov <andrey.matyukov@intel.com> | 2020-12-08 22:53:39 +0300 |
|---|---|---|
| committer | Pauli <pauli@openssl.org> | 2021-11-19 12:50:34 +1000 |
| commit | f87b4c4ea67393c9269663ed40a7ea3463cc59d3 (patch) | |
| tree | 4af4c0fd0415e6cc19e812b0eead726ed948661f /crypto/bn/build.info | |
| parent | e67edf60f2e9be6e5f5465b52d01aa26bf715280 (diff) | |
Dual 1536/2048-bit exponentiation optimization for Intel IceLake CPU
It uses AVX512_IFMA + AVX512_VL (with 256-bit wide registers) ISA to
keep lower power license.
Reviewed-by: Matt Caswell <matt@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/14908)
Diffstat (limited to 'crypto/bn/build.info')
| -rw-r--r-- | crypto/bn/build.info | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/crypto/bn/build.info b/crypto/bn/build.info index 9330274aef..b0fcb7ab97 100644 --- a/crypto/bn/build.info +++ b/crypto/bn/build.info @@ -24,7 +24,7 @@ IF[{- !$disabled{asm} -}] $BNASM_x86_64=\ x86_64-mont.s x86_64-mont5.s x86_64-gf2m.s rsaz_exp.c rsaz-x86_64.s \ - rsaz-avx2.s rsaz_exp_x2.c rsaz-avx512.s + rsaz-avx2.s rsaz_exp_x2.c rsaz-2k-avx512.s rsaz-3k-avx512.s rsaz-4k-avx512.s IF[{- $config{target} !~ /^VC/ -}] $BNASM_x86_64=asm/x86_64-gcc.c $BNASM_x86_64 ELSE @@ -160,7 +160,9 @@ GENERATE[x86_64-mont5.s]=asm/x86_64-mont5.pl GENERATE[x86_64-gf2m.s]=asm/x86_64-gf2m.pl GENERATE[rsaz-x86_64.s]=asm/rsaz-x86_64.pl GENERATE[rsaz-avx2.s]=asm/rsaz-avx2.pl -GENERATE[rsaz-avx512.s]=asm/rsaz-avx512.pl +GENERATE[rsaz-2k-avx512.s]=asm/rsaz-2k-avx512.pl +GENERATE[rsaz-3k-avx512.s]=asm/rsaz-3k-avx512.pl +GENERATE[rsaz-4k-avx512.s]=asm/rsaz-4k-avx512.pl GENERATE[bn-ia64.s]=asm/ia64.S GENERATE[ia64-mont.s]=asm/ia64-mont.pl |