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authorAndy Polyakov <appro@openssl.org>2014-05-04 10:55:49 +0200
committerAndy Polyakov <appro@openssl.org>2014-05-04 10:55:49 +0200
commit4afa9f033dd58465b4c2d119a9d8cd737edeba26 (patch)
tree322c3cd2d3665909990b7e747108232770920091 /crypto/armv4cpuid.S
parent16ba70746b3bd9d1bd17cf7135c00ff1e47dfcfe (diff)
crypto/armcap.c: detect ARMv8 capabilities [in 32-bit build].
Diffstat (limited to 'crypto/armv4cpuid.S')
-rw-r--r--crypto/armv4cpuid.S28
1 files changed, 28 insertions, 0 deletions
diff --git a/crypto/armv4cpuid.S b/crypto/armv4cpuid.S
index 2d618deaa4..edd619800f 100644
--- a/crypto/armv4cpuid.S
+++ b/crypto/armv4cpuid.S
@@ -18,6 +18,34 @@ _armv7_tick:
.word 0xe12fff1e @ bx lr
.size _armv7_tick,.-_armv7_tick
+.global _armv8_aes_probe
+.type _armv8_aes_probe,%function
+_armv8_aes_probe:
+ .word 0xf3b00300 @ aese.8 q0,q0
+ .word 0xe12fff1e @ bx lr
+.size _armv8_aes_probe,.-_armv8_aes_probe
+
+.global _armv8_sha1_probe
+.type _armv8_sha1_probe,%function
+_armv8_sha1_probe:
+ .word 0xf2000c40 @ sha1c.32 q0,q0,q0
+ .word 0xe12fff1e @ bx lr
+.size _armv8_sha1_probe,.-_armv8_sha1_probe
+
+.global _armv8_sha256_probe
+.type _armv8_sha256_probe,%function
+_armv8_sha256_probe:
+ .word 0xf3000c40 @ sha256h.32 q0,q0,q0
+ .word 0xe12fff1e @ bx lr
+.size _armv8_sha256_probe,.-_armv8_sha256_probe
+.global _armv8_pmull_probe
+.type _armv8_pmull_probe,%function
+_armv8_pmull_probe:
+ .word 0xf2a00e00 @ vmull.p64 q0,d0,d0
+ .word 0xe12fff1e @ bx lr
+.size _armv8_pmull_probe,.-_armv8_pmull_probe
+
+.align 5
.global OPENSSL_atomic_add
.type OPENSSL_atomic_add,%function
OPENSSL_atomic_add: