diff options
| author | Andy Polyakov <appro@openssl.org> | 2016-04-23 19:10:04 +0200 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2016-04-25 11:50:54 +0200 |
| commit | 299ccadcdb99001c618d188fb243c1caaaa86a1c (patch) | |
| tree | cdb80f1346d4357335e55ca4440946834a154b28 | |
| parent | a82a9f71ad0149380a680cae4c0cc693e6324679 (diff) | |
crypto/sparc_arch.h: reserve more SPARCv9 capability bits.
Reviewed-by: Richard Levitte <levitte@openssl.org>
| -rw-r--r-- | crypto/sparc_arch.h | 9 | ||||
| -rw-r--r-- | crypto/sparcv9cap.c | 17 |
2 files changed, 20 insertions, 6 deletions
diff --git a/crypto/sparc_arch.h b/crypto/sparc_arch.h index 6f8969fc25..5bcdd9fc71 100644 --- a/crypto/sparc_arch.h +++ b/crypto/sparc_arch.h @@ -5,12 +5,16 @@ # define SPARCV9_PREFER_FPU (1<<1) # define SPARCV9_VIS1 (1<<2) # define SPARCV9_VIS2 (1<<3)/* reserved */ -# define SPARCV9_FMADD (1<<4)/* reserved for SPARC64 V */ +# define SPARCV9_FMADD (1<<4) # define SPARCV9_BLK (1<<5)/* VIS1 block copy */ # define SPARCV9_VIS3 (1<<6) # define SPARCV9_RANDOM (1<<7) # define SPARCV9_64BIT_STACK (1<<8) # define SPARCV9_FJAESX (1<<9)/* Fujitsu SPARC64 X AES */ +# define SPARCV9_FJDESX (1<<10)/* Fujitsu SPARC64 X DES, reserved */ +# define SPARCV9_FJHPCACE (1<<11)/* Fujitsu HPC-ACE, reserved */ +# define SPARCV9_IMA (1<<13)/* reserved */ +# define SPARCV9_VIS4 (1<<14)/* reserved */ /* * OPENSSL_sparcv9cap_P[1] is copy of Compatibility Feature Register, @@ -29,6 +33,9 @@ # define CFR_MONTMUL 0x00000200/* Supports MONTMUL opcodes */ # define CFR_MONTSQR 0x00000400/* Supports MONTSQR opcodes */ # define CFR_CRC32C 0x00000800/* Supports CRC32C opcodes */ +# define CFR_XMPMUL 0x00001000/* Supports XMPMUL opcodes */ +# define CFR_XMONTMUL 0x00002000/* Supports XMONTMUL opcodes */ +# define CFR_XMONTSQR 0x00004000/* Supports XMONTSQR opcodes */ # if defined(OPENSSL_PIC) && !defined(__PIC__) # define __PIC__ diff --git a/crypto/sparcv9cap.c b/crypto/sparcv9cap.c index e1e6d73955..30c384b04d 100644 --- a/crypto/sparcv9cap.c +++ b/crypto/sparcv9cap.c @@ -149,17 +149,24 @@ void OPENSSL_cpuid_setup(void) unsigned int vec[1]; if (getisax (vec,1)) { - if (vec[0]&0x0020) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1; - if (vec[0]&0x0040) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2; - if (vec[0]&0x0080) OPENSSL_sparcv9cap_P[0] |= SPARCV9_BLK; - if (vec[0]&0x0100) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD; - if (vec[0]&0x0400) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3; + if (vec[0]&0x00020) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS1; + if (vec[0]&0x00040) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS2; + if (vec[0]&0x00080) OPENSSL_sparcv9cap_P[0] |= SPARCV9_BLK; + if (vec[0]&0x00100) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD; + if (vec[0]&0x00400) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3; + if (vec[0]&0x01000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJHPCACE; + if (vec[0]&0x02000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJDESX; + if (vec[0]&0x08000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_IMA; if (vec[0]&0x10000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJAESX; + if (vec[1]&0x00008) OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS4; /* reconstruct %cfr copy */ OPENSSL_sparcv9cap_P[1] = (vec[0]>>17)&0x3ff; OPENSSL_sparcv9cap_P[1] |= (OPENSSL_sparcv9cap_P[1]&CFR_MONTMUL)<<1; if (vec[0]&0x20000000) OPENSSL_sparcv9cap_P[1] |= CFR_CRC32C; + if (vec[1]&0x00000020) OPENSSL_sparcv9cap_P[1] |= CFR_XMPMUL; + if (vec[1]&0x00000040) + OPENSSL_sparcv9cap_P[1] |= CFR_XMONTMUL|CFR_XMONTSQR; /* Some heuristics */ /* all known VIS2-capable CPUs have unprivileged tick counter */ |