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authorMichael Raskin <7c6f434c@mail.ru>2013-10-29 10:56:33 +0400
committerMichael Raskin <7c6f434c@mail.ru>2013-10-29 10:56:33 +0400
commit22ddf66b54396f865ae1c1df6a366640039c20c6 (patch)
treeb16622d756ba5b91f3c5a568822e72fb75384e4a /pkgs/development/lisp-modules/from-quicklisp
parenta976962d6cb87ffb946956fe58a5dfd5742f769e (diff)
Adding a facility to generate Lisp module definitions from QuickLisp; no sane update facility yet; adding Esrap-PEG as a test
Diffstat (limited to 'pkgs/development/lisp-modules/from-quicklisp')
-rwxr-xr-xpkgs/development/lisp-modules/from-quicklisp/asdf-description.sh16
-rwxr-xr-xpkgs/development/lisp-modules/from-quicklisp/barebones-quicklisp-expression.sh78
-rwxr-xr-xpkgs/development/lisp-modules/from-quicklisp/quicklisp-beta-env.sh16
-rwxr-xr-xpkgs/development/lisp-modules/from-quicklisp/quicklisp-dependencies.sh11
-rw-r--r--pkgs/development/lisp-modules/from-quicklisp/tmp.nix0
5 files changed, 121 insertions, 0 deletions
diff --git a/pkgs/development/lisp-modules/from-quicklisp/asdf-description.sh b/pkgs/development/lisp-modules/from-quicklisp/asdf-description.sh
new file mode 100755
index 000000000000..6c240d15c76e
--- /dev/null
+++ b/pkgs/development/lisp-modules/from-quicklisp/asdf-description.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+[ -z "$NIX_QUICKLISP_DIR" ] && {
+ export NIX_QUICKLISP_DIR="$(mktemp -d --tmpdir nix-quicklisp.XXXXXX)"
+}
+
+[ -f "$NIX_QUICKLISP_DIR/setup.lisp" ] || {
+ "$(dirname "$0")/quicklisp-beta-env.sh" "$NIX_QUICKLISP_DIR" &> /dev/null < /dev/null
+}
+
+name="$1"
+
+sbcl --noinform --load "$NIX_QUICKLISP_DIR"/setup.lisp --eval "(ql:quickload :$name)" \
+ --eval "(format t \"~a~%\" (or (asdf::system-description (asdf::find-system \"$name\")) \"\"))" \
+ --eval '(quit)' --script |
+ tee /dev/stderr | tail -n 1
diff --git a/pkgs/development/lisp-modules/from-quicklisp/barebones-quicklisp-expression.sh b/pkgs/development/lisp-modules/from-quicklisp/barebones-quicklisp-expression.sh
new file mode 100755
index 000000000000..61c00eb92ae8
--- /dev/null
+++ b/pkgs/development/lisp-modules/from-quicklisp/barebones-quicklisp-expression.sh
@@ -0,0 +1,78 @@
+#! /bin/sh
+
+name="$1"
+
+nix-instantiate "$(dirname "$0")"/../../../../ -A "lispPackages.$name" > /dev/null && exit
+[ "$NIX_LISP_PACKAGES_DEFINED" != "${NIX_LISP_PACKAGES_DEFINED/$name/@@}" ] && exit
+
+NIX_LISP_PACKAGES_DEFINED="$NIX_LISP_PACKAGES_DEFINED $1 "
+
+[ -z "$NIX_QUICKLISP_DIR" ] && {
+ export NIX_QUICKLISP_DIR="$(mktemp -d --tmpdir nix-quicklisp.XXXXXX)"
+}
+
+[ -f "$NIX_QUICKLISP_DIR/setup.lisp" ] || {
+ "$(dirname "$0")/quicklisp-beta-env.sh" "$NIX_QUICKLISP_DIR" &> /dev/null < /dev/null
+}
+
+description="$("$(dirname "$0")/asdf-description.sh" "$name")"
+[ -z "$description" ] && {
+ description="$(curl -L https://github.com/quicklisp/quicklisp-projects/raw/master/"$name"/description.txt)"
+ [ "$(echo "$description" | wc -l)" -gt 10 ] && description=""
+}
+
+dependencies="$("$(dirname "$0")/quicklisp-dependencies.sh" "$name" | xargs)"
+ql_src="$(curl -L https://github.com/quicklisp/quicklisp-projects/raw/master/"$name"/source.txt)"
+ql_src_type="${ql_src%% *}"
+url="${ql_src##* }"
+
+[ "$ql_src_type" = git ] && {
+ fetcher="pkgs.fetchgit"
+ [ "${url#git://github.com/}" != "$url" ] && {
+ url="${url/git:/https:}"
+ url="${url%.git}"
+ rev=$("$(dirname "$0")/../../../build-support/upstream-updater/urls-from-page.sh" "$url/commits" | grep /commit/ | head -n 1 | xargs basename)
+ hash=$("$(dirname "$0")/../../../build-support/fetchgit/nix-prefetch-git" "$url" "$rev")
+ version="git-$(date +%Y%m%d)";
+ }
+ [ "${url#git://common-lisp.net/}" != "$url" ] && {
+ http_repo_url="$url"
+ http_repo_url="${http_repo_url/git:/http:}"
+ http_repo_url="${http_repo_url/\/projects\// /r/projects/}"
+ http_repo_head="$http_repo_url/refs/heads/master"
+ echo "$http_repo_head" >&2
+ rev=$(curl -L "$http_repo_head");
+ hash=$("$(dirname "$0")/../../../build-support/fetchgit/nix-prefetch-git" "$url" "$rev")
+ version="git-$(date +%Y%m%d)";
+ }
+}
+
+[ "$ql_src_type" = cvs ] && {
+ fetcher="pkgs.fetchcvs"
+ date="$(date -d yesterday +%Y-%m-%d)"
+ version="cvs-$date"
+ module="${module:-$name}"
+ hash=$(USE_DATE=1 "$(dirname "$0")/../../../build-support/fetchcvs/nix-prefetch-cvs" "$url" "$module" "$date")
+ cvsRoot="$url"
+ unset url
+}
+
+cat << EOF
+
+ $name = buildLispPackage rec {
+ baseName = "$name";
+ version = "${version:-\${Set me //}";
+ description = "$description";
+ deps = [$dependencies];
+ src = ${fetcher:-pkgs.fetchurl} {
+ ${url:+url = ''$url'';}
+ sha256 = "${hash:-0000000000000000000000000000000000000000000000000000000000000000}";
+ ${rev:+rev = ''$rev'';}
+ ${date:+date = ''$date'';}
+ ${module:+module = ''$module'';}
+ ${cvsRoot:+cvsRoot = ''$cvsRoot'';}
+ };
+ };
+EOF
+
+for i in $dependencies; do "$0" "$i"; done
diff --git a/pkgs/development/lisp-modules/from-quicklisp/quicklisp-beta-env.sh b/pkgs/development/lisp-modules/from-quicklisp/quicklisp-beta-env.sh
new file mode 100755
index 000000000000..32fbbe4bb2bc
--- /dev/null
+++ b/pkgs/development/lisp-modules/from-quicklisp/quicklisp-beta-env.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+WORK_DIR=$(mktemp -d "/tmp/ql-venv-XXXXXX")
+mkdir -p "${1:-.}"
+TARGET="$(cd "${1:-.}"; pwd)"
+
+curl http://beta.quicklisp.org/quicklisp.lisp > "$WORK_DIR/ql.lisp"
+
+sbcl --noinform \
+ --load "$WORK_DIR/ql.lisp" \
+ --eval "(quicklisp-quickstart:install :path \"$TARGET/\")" \
+ --eval "(cl-user::quit)" \
+ --script
+
+
+rm -rf "$WORK_DIR"
diff --git a/pkgs/development/lisp-modules/from-quicklisp/quicklisp-dependencies.sh b/pkgs/development/lisp-modules/from-quicklisp/quicklisp-dependencies.sh
new file mode 100755
index 000000000000..24efbdd3e16e
--- /dev/null
+++ b/pkgs/development/lisp-modules/from-quicklisp/quicklisp-dependencies.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+[ -z "$NIX_QUICKLISP_DIR" ] && {
+ export NIX_QUICKLISP_DIR="$(mktemp -d --tmpdir nix-quicklisp.XXXXXX)"
+}
+
+[ -f "$NIX_QUICKLISP_DIR/setup.lisp" ] || {
+ "$(dirname "$0")/quicklisp-beta-env.sh" "$NIX_QUICKLISP_DIR" &> /dev/null < /dev/null
+}
+
+sbcl --noinform --eval "(with-output-to-string (*standard-output*) (load \"$NIX_QUICKLISP_DIR/setup.lisp\"))" --eval "(with-output-to-string (*standard-output*) (with-output-to-string (*error-output*) (with-output-to-string (*trace-output*) (ql:quickload :$1))))" --eval "(format t \"~{~a~%~}\" (mapcar 'ql::name (mapcar 'car (cdr (ql::dependency-tree \"$1\")))))" --eval '(quit)' --script
diff --git a/pkgs/development/lisp-modules/from-quicklisp/tmp.nix b/pkgs/development/lisp-modules/from-quicklisp/tmp.nix
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/pkgs/development/lisp-modules/from-quicklisp/tmp.nix
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/*
 * SuperH Timer Support - MTU2
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

struct sh_mtu2_device;

struct sh_mtu2_channel {
	struct sh_mtu2_device *mtu;
	unsigned int index;

	void __iomem *base;

	struct clock_event_device ced;
};

struct sh_mtu2_device {
	struct platform_device *pdev;

	void __iomem *mapbase;
	struct clk *clk;

	raw_spinlock_t lock; /* Protect the shared registers */

	struct sh_mtu2_channel *channels;
	unsigned int num_channels;

	bool has_clockevent;
};

#define TSTR -1 /* shared register */
#define TCR  0 /* channel register */
#define TMDR 1 /* channel register */
#define TIOR 2 /* channel register */
#define TIER 3 /* channel register */
#define TSR  4 /* channel register */
#define TCNT 5 /* channel register */
#define TGR  6 /* channel register */

#define TCR_CCLR_NONE		(0 << 5)
#define TCR_CCLR_TGRA		(1 << 5)
#define TCR_CCLR_TGRB		(2 << 5)
#define TCR_CCLR_SYNC		(3 << 5)
#define TCR_CCLR_TGRC		(5 << 5)
#define TCR_CCLR_TGRD		(6 << 5)
#define TCR_CCLR_MASK		(7 << 5)
#define TCR_CKEG_RISING		(0 << 3)
#define TCR_CKEG_FALLING	(1 << 3)
#define TCR_CKEG_BOTH		(2 << 3)
#define TCR_CKEG_MASK		(3 << 3)
/* Values 4 to 7 are channel-dependent */
#define TCR_TPSC_P1		(0 << 0)
#define TCR_TPSC_P4		(1 << 0)
#define TCR_TPSC_P16		(2 << 0)
#define TCR_TPSC_P64		(3 << 0)
#define TCR_TPSC_CH0_TCLKA	(4 << 0)
#define TCR_TPSC_CH0_TCLKB	(5 << 0)
#define TCR_TPSC_CH0_TCLKC	(6 << 0)
#define TCR_TPSC_CH0_TCLKD	(7 << 0)
#define TCR_TPSC_CH1_TCLKA	(4 << 0)
#define TCR_TPSC_CH1_TCLKB	(5 << 0)
#define TCR_TPSC_CH1_P256	(6 << 0)
#define TCR_TPSC_CH1_TCNT2	(7 << 0)
#define TCR_TPSC_CH2_TCLKA	(4 << 0)
#define TCR_TPSC_CH2_TCLKB	(5 << 0)
#define TCR_TPSC_CH2_TCLKC	(6 << 0)
#define TCR_TPSC_CH2_P1024	(7 << 0)
#define TCR_TPSC_CH34_P256	(4 << 0)
#define TCR_TPSC_CH34_P1024	(5 << 0)
#define TCR_TPSC_CH34_TCLKA	(6 << 0)
#define TCR_TPSC_CH34_TCLKB	(7 << 0)
#define TCR_TPSC_MASK		(7 << 0)

#define TMDR_BFE		(1 << 6)
#define TMDR_BFB		(1 << 5)
#define TMDR_BFA		(1 << 4)
#define TMDR_MD_NORMAL		(0 << 0)
#define TMDR_MD_PWM_1		(2 << 0)
#define TMDR_MD_PWM_2		(3 << 0)
#define TMDR_MD_PHASE_1		(4 << 0)
#define TMDR_MD_PHASE_2		(5 << 0)
#define TMDR_MD_PHASE_3		(6 << 0)
#define TMDR_MD_PHASE_4		(7 << 0)
#define TMDR_MD_PWM_SYNC	(8 << 0)
#define TMDR_MD_PWM_COMP_CREST	(13 << 0)
#define TMDR_MD_PWM_COMP_TROUGH	(14 << 0)
#define TMDR_MD_PWM_COMP_BOTH	(15 << 0)
#define TMDR_MD_MASK		(15 << 0)

#define TIOC_IOCH(n)		((n) << 4)
#define TIOC_IOCL(n)		((n) << 0)
#define TIOR_OC_RETAIN		(0 << 0)
#define TIOR_OC_0_CLEAR		(1 << 0)
#define TIOR_OC_0_SET		(2 << 0)
#define TIOR_OC_0_TOGGLE	(3 << 0)
#define TIOR_OC_1_CLEAR		(5 << 0)
#define TIOR_OC_1_SET		(6 << 0)
#define TIOR_OC_1_TOGGLE	(7 << 0)
#define TIOR_IC_RISING		(8 << 0)
#define TIOR_IC_FALLING		(9 << 0)
#define TIOR_IC_BOTH		(10 << 0)
#define TIOR_IC_TCNT		(12 << 0)
#define TIOR_MASK		(15 << 0)

#define TIER_TTGE		(1 << 7)
#define TIER_TTGE2		(1 << 6)
#define TIER_TCIEU		(1 << 5)
#define TIER_TCIEV		(1 << 4)
#define TIER_TGIED		(1 << 3)
#define TIER_TGIEC		(1 << 2)
#define TIER_TGIEB		(1 << 1)
#define TIER_TGIEA		(1 << 0)

#define TSR_TCFD		(1 << 7)
#define TSR_TCFU		(1 << 5)
#define TSR_TCFV		(1 << 4)
#define TSR_TGFD		(1 << 3)
#define TSR_TGFC		(1 << 2)
#define TSR_TGFB		(1 << 1)
#define TSR_TGFA		(1 << 0)

static unsigned long mtu2_reg_offs[] = {
	[TCR] = 0,
	[TMDR] = 1,
	[TIOR] = 2,
	[TIER] = 4,
	[TSR] = 5,
	[TCNT] = 6,
	[TGR] = 8,
};

static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
{
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(ch->mtu->mapbase + 0x280);

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		return ioread16(ch->base + offs);
	else
		return ioread8(ch->base + offs);
}

static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
				unsigned long value)
{
	unsigned long offs;

	if (reg_nr == TSTR)
		return iowrite8(value, ch->mtu->mapbase + 0x280);

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		iowrite16(value, ch->base + offs);
	else
		iowrite8(value, ch->base + offs);
}

static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
{
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&ch->mtu->lock, flags);
	value = sh_mtu2_read(ch, TSTR);

	if (start)
		value |= 1 << ch->index;
	else
		value &= ~(1 << ch->index);

	sh_mtu2_write(ch, TSTR, value);
	raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
}

static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
{
	unsigned long periodic;
	unsigned long rate;
	int ret;

	pm_runtime_get_sync(&ch->mtu->pdev->dev);
	dev_pm_syscore_device(&ch->mtu->pdev->dev, true);

	/* enable clock */
	ret = clk_enable(ch->mtu->clk);
	if (ret) {
		dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
			ch->index);
		return ret;
	}

	/* make sure channel is disabled */
	sh_mtu2_start_stop_ch(ch, 0);

	rate = clk_get_rate(ch->mtu->clk) / 64;
	periodic = (rate + HZ/2) / HZ;

	/*
	 * "Periodic Counter Operation"
	 * Clear on TGRA compare match, divide clock by 64.
	 */
	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
		      TIOC_IOCL(TIOR_OC_0_CLEAR));
	sh_mtu2_write(ch, TGR, periodic);
	sh_mtu2_write(ch, TCNT, 0);
	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
	sh_mtu2_write(ch, TIER, TIER_TGIEA);

	/* enable channel */
	sh_mtu2_start_stop_ch(ch, 1);

	return 0;
}

static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
{
	/* disable channel */
	sh_mtu2_start_stop_ch(ch, 0);

	/* stop clock */
	clk_disable(ch->mtu->clk);

	dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
	pm_runtime_put(&ch->mtu->pdev->dev);
}

static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
{
	struct sh_mtu2_channel *ch = dev_id;

	/* acknowledge interrupt */
	sh_mtu2_read(ch, TSR);
	sh_mtu2_write(ch, TSR, ~TSR_TGFA);

	/* notify clockevent layer */
	ch->ced.event_handler(&ch->ced);
	return IRQ_HANDLED;
}

static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_mtu2_channel, ced);
}

static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		sh_mtu2_disable(ch);
		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		dev_info(&ch->mtu->pdev->dev,
			 "ch%u: used for periodic clock events\n", ch->index);
		sh_mtu2_enable(ch);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
			sh_mtu2_disable(ch);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev