diff options
author | Moritz Ulrich <moritz@tarn-vedra.de> | 2016-05-28 15:41:10 +0200 |
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committer | Moritz Ulrich <moritz@tarn-vedra.de> | 2016-05-28 15:41:10 +0200 |
commit | 7b2fab05f385a445811b60fe0dde37e59b4c7e81 (patch) | |
tree | d447d60e8fd0af17990553a945746a670356cd65 /pkgs/development/compilers | |
parent | 373455e237d7b9fff27dd2d94682084dc95d9a23 (diff) | |
parent | 7ae681920cb92f15a0fc2152452ec22622741a7a (diff) |
Merge pull request #15606 from dvc94ch/fpga-toolchain-updates
FPGA toolchain updates
Diffstat (limited to 'pkgs/development/compilers')
-rw-r--r-- | pkgs/development/compilers/arachne-pnr/default.nix | 6 | ||||
-rw-r--r-- | pkgs/development/compilers/yosys/default.nix | 11 |
2 files changed, 8 insertions, 9 deletions
diff --git a/pkgs/development/compilers/arachne-pnr/default.nix b/pkgs/development/compilers/arachne-pnr/default.nix index 7926bf273acb..76df7c2828f7 100644 --- a/pkgs/development/compilers/arachne-pnr/default.nix +++ b/pkgs/development/compilers/arachne-pnr/default.nix @@ -2,13 +2,13 @@ stdenv.mkDerivation rec { name = "arachne-pnr-${version}"; - version = "2015.12.29"; + version = "2016.05.21"; src = fetchFromGitHub { owner = "cseed"; repo = "arachne-pnr"; - rev = "1a4fdf96a7fd08806c032d41a2443c8e17c72c80"; - sha256 = "1dj7ycffwkmlsh12117fbybkdfnlhxbbxkbfgwfyvcgmg3cacgl1"; + rev = "6b8336497800782f2f69572d40702b60423ec67f"; + sha256 = "11hg17f4lp8azc0ir0i473fz9c0dra82r4fn45cr3amd57v00qbf"; }; preBuild = '' diff --git a/pkgs/development/compilers/yosys/default.nix b/pkgs/development/compilers/yosys/default.nix index cfaabb0a71a9..7c44e03d7010 100644 --- a/pkgs/development/compilers/yosys/default.nix +++ b/pkgs/development/compilers/yosys/default.nix @@ -2,21 +2,21 @@ stdenv.mkDerivation rec { name = "yosys-${version}"; - version = "2015.12.29"; + version = "2016.05.21"; srcs = [ (fetchFromGitHub { owner = "cliffordwolf"; repo = "yosys"; - rev = "1d62f8710f04fec405ef79b9e9a4a031afcf7d42"; - sha256 = "0q1dk9in3gmrihb58pjckncx56lj7y4b6y34jgb68f0fh91fdvfx"; + rev = "8e9e793126a2772eed4b041bc60415943c71d5ee"; + sha256 = "1s0x7n7qh2qbfc0d7p4q10fvkr61jdqgyqzijr422rabh9zl4val"; name = "yosys"; }) (fetchFromBitbucket { owner = "alanmi"; repo = "abc"; - rev = "c3698e053a7a"; - sha256 = "05p0fvbr7xvb6w3d7j2r6gynr3ljb6r5q6jvn2zs3ysn2b003qwd"; + rev = "d9559ab"; + sha256 = "08far669khb65kfpqvjqmqln473j949ak07xibfdjdmiikcy533i"; name = "abc"; }) ]; @@ -37,7 +37,6 @@ stdenv.mkDerivation rec { Yosys is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. - Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ |