[
{
"PublicDescription": "Demand Data Read requests that hit L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"SampleAfterValue": "200003",
"BriefDescription": "Demand Data Read requests",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "RFO requests that hit L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "RFO requests that hit L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "RFO requests that miss L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts all L2 store RFO requests.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0xc",
"EventName": "L2_RQSTS.ALL_RFO",
"SampleAfterValue": "200003",
"BriefDescription": "RFO requests to L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "L2 cache misses when fetching instructions",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts all L2 code requests.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"SampleAfterValue": "200003",
"BriefDescription": "L2 code requests",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "L2_RQSTS.PF_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "L2_RQSTS.PF_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"PublicDescription": "Counts all L2 HW prefetcher requests.",
"EventCode": "0x24",
"Counter": "0,1,2,3",
"UMask": "0xc0",
"EventName": "L2_RQSTS.ALL_PF",
"SampleAfterValue": "200003",
"BriefDescription"