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[
{
"EventCode": "0x3013E",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)"
},
{
"EventCode": "0x4F056",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache"
},
{
"EventCode": "0x24158",
"EventName": "PM_MRK_INST",
"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens"
},
{
"EventCode": "0x1E046",
"EventName": "PM_DPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x3C04A",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load"
},
{
"EventCode": "0x2C01C",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)"
},
{
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{
"EventCode": "0x2E050",
"EventName": "PM_DARQ0_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use"
},
{
"EventCode": "0x2D02E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{
"EventCode": "0x3F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{
"EventCode": "0x2E01E",
"EventName": "PM_CMPLU_STALL_NTC_FLUSH",
"BriefDescription": "Completion stall due to ntc flush"
},
{
"EventCode": "0x1F14C",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only"
},
{
"EventCode": "0x3F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x4D058",
"EventName": "PM_VECTOR_FLOP_CMPL",
"BriefDescription": "Vector FP instruction completed"
},
{
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)"
},
{
"EventCode": "0x4404E",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch"
},
{
"EventCode": "0x3003A",
"EventName": "PM_CMPLU_STALL_EXCEPTION",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete"
},
{
"EventCode": "0x4F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x3E044",
"EventName": "PM_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x300F6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load"
},
{
"EventCode": "0x1415E",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
},
{
"EventCode": "0x1E052",
"EventName": "PM_CMPLU_STALL_SLB",
"BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
},
{
"EventCode": "0x4404C",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)"
},
{
"EventCode": "0x3000E",
"EventName": "PM_FXU_1PLUS_BUSY",
"BriefDescription": "At least one of the 4 FXU units is busy"
},
{
"EventCode": "0x2C048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load"
},
{
"EventCode": "0x3000A",
"EventName": "PM_CMPLU_STALL_PM",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle"
},
{
"EventCode": "0x1504E",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request"
},
{
"EventCode": "0x1C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load"
},
{
"EventCode": "0x30008",
"EventName": "PM_DISP_STARVED",
"BriefDescription": "Dispatched Starved"
},
{
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)"
},
{
"EventCode": "0x4000C",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A"
},
{
"EventCode": "0x3C050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load"
},
{
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request"
},
{
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued"
},
{
"EventCode": "0x1C046",
"EventName": "PM_DATA_FROM_L31_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load"
},
{
"EventCode": "0x2C044",
"EventName": "PM_DATA_FROM_L31_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load"
},
{
"EventCode": "0x2C04A",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load"
},
{
"EventCode": "0x24044",
"EventName": "PM_INST_FROM_L31_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)"
},
{
"EventCode": "0x4C050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load"
},
{
"EventCode": "0x2C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load"
},
{
"EventCode": "0x2F148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x4D01A",
"EventName": "PM_CMPLU_STALL_EIEIO",
"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2"
},
{
"EventCode": "0x4F14E",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{
"EventCode": "0x4F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3",
|