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|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* ALSA SoC SPDIF Audio Layer
*
* Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
* Copyright 2015 Marcus Cooper <codekipper@gmail.com>
*
* Based on the Allwinner SDK driver, released under the GPL.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/regmap.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define SUN4I_SPDIF_CTL (0x00)
#define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
#define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
#define SUN4I_SPDIF_CTL_GEN BIT(1)
#define SUN4I_SPDIF_CTL_RESET BIT(0)
#define SUN4I_SPDIF_TXCFG (0x04)
#define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
#define SUN4I_SPDIF_TXCFG_ASS BIT(17)
#define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
#define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
#define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
#define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
#define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
#define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
#define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
#define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
#define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
#define SUN4I_SPDIF_RXCFG (0x08)
#define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
#define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
#define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
#define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
#define SUN4I_SPDIF_TXFIFO (0x0C)
#define SUN4I_SPDIF_RXFIFO (0x10)
#define SUN4I_SPDIF_FCTL (0x14)
#define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
#define SUN4I_SPDIF_FCTL_FTX BIT(17)
#define SUN4I_SPDIF_FCTL_FRX BIT(16)
#define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
#define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
#define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
#define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
#define SUN4I_SPDIF_FCTL_TXIM BIT(2)
#define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
#define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
#define SUN50I_H6_SPDIF_FCTL (0x14)
#define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
#define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
#define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
#define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
#define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
#define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
#define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
#define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
#define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
#define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
#define SUN4I_SPDIF_FSTA (0x18)
#define SUN4I_SPDIF_FSTA_TXE BIT(14)
#define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
#define SUN4I_SPDIF_FSTA_RXA BIT(6)
#define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
#define SUN4I_SPDIF_INT (0x1C)
#define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
#define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
#define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
#define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
#define SUN4I_SPDIF_INT_TXUIEN BIT(6)
#define SUN4I_SPDIF_INT_TXOIEN BIT(5)
#define SUN4I_SPDIF_INT_TXEIEN BIT(4)
#define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
#define SUN4I_SPDIF_INT_RXOIEN BIT(1)
#define SUN4I_SPDIF_INT_RXAIEN BIT(0)
#define SUN4I_SPDIF_ISTA (0x20)
#define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
#define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
#define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
#define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
#define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
#define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
#define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
#define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
#define SUN8I_SPDIF_TXFIFO (0x20)
#define SUN4I_SPDIF_TXCNT (0x24)
#define SUN4I_SPDIF_RXCNT (0x28)
#define SUN4I_SPDIF_TXCHSTA0 (0x2C)
#define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
#define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
#define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
#define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
#define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
#define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
#define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
#define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
#define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
#define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
#define SUN4I_SPDIF_TXCHSTA1 (0x30)
#define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
#define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
#define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
#define SUN4I_SPDIF_RXCHSTA0 (0x34)
#define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
#define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
#define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
#define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
#define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
#define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
#define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
#define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
#define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
#define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
#define SUN4I_SPDIF_RXCHSTA1 (0x38)
#define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
#define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
#define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
#define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
/* Defines for Sampling Frequency */
#define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
#define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
#define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
#define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
#define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
#define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
#define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
#define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
#define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
#define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
#define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
/**
* struct sun4i_spdif_quirks - Differences between SoC variants.
*
* @reg_dac_tx_data: TX FIFO offset for DMA config.
* @has_reset: SoC needs reset deasserted.
* @val_fctl_ftx: TX FIFO flush bitmask.
*/
struct sun4i_spdif_quirks {
unsigned int reg_dac_txdata;
bool has_reset;
unsigned int val_fctl_ftx;
};
struct sun4i_spdif_dev {
struct platform_device *pdev;
struct clk *spdif_clk;
struct clk *apb_clk;
struct reset_control *rst;
struct snd_soc_dai_driver cpu_dai_drv;
struct regmap *regmap;
struct snd_dmaengine_dai_dma_data dma_params_tx;
const struct sun4i_spdif_quirks *quirks;
};
static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
{
const struct sun4i_spdif_quirks *quirks = host->quirks;
/* soft reset SPDIF */
regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
/* flush TX FIFO */
regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
quirks->val_fctl_ftx, quirks->val_fctl_ftx);
/* clear TX counter */
regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
}
static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
struct sun4i_spdif_dev *host)
{
if (substream->runtime->channels == 1)
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_SINGLEMOD,
SUN4I_SPDIF_TXCFG_SINGLEMOD);
/* SPDIF TX ENABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
/* DRQ ENABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
/* Global enable */
regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
}
static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
struct sun4i_spdif_dev *host)
{
/* SPDIF TX DISABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
SUN4I_SPDIF_TXCFG_TXEN, 0);
/* DRQ DISABLE */
regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
SUN4I_SPDIF_INT_TXDRQEN, 0);
/* Global disable */
regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
SUN4I_SPDIF_CTL_GEN, 0);
}
static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
sun4i_spdif_configure(host);
return 0;
}
static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
int ret = 0;
int fmt;
unsigned long rate = params_rate(params);
u32 mclk_div = 0;
unsigned int mclk = 0;
u32 reg_val;
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
struct platform_device *pdev = host->pdev;
/* Add the PCM and raw data select interface */
switch (params_channels(params)) {
case 1: /* PCM mode */
case 2:
fmt = 0;
break;
case 4: /* raw data mode */
fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
break;
default:
return -EINVAL;
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
break;
case SNDRV_PCM_FORMAT_S24_LE:
fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
break;
default:
return -EINVAL;
}
switch (rate) {
case 22050:
case 44100:
case 88200:
case 176400:
mclk = 22579200;
break;
case 24000:
case 32000:
case 48000:
case 96000:
case 192000:
mclk = 24576000;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(host->spdif_clk, mclk);
if (ret < 0) {
dev_err(&pdev->dev,
"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
return ret;
}
regmap_update_bits
|