// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Andrea Venturi
* Andrea Venturi <be17068@iperbole.bo.it>
*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <maxime.ripard@free-electrons.com>
*/
#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#define SUN4I_I2S_CTRL_REG 0x00
#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
#define SUN4I_I2S_CTRL_TX_EN BIT(2)
#define SUN4I_I2S_CTRL_RX_EN BIT(1)
#define SUN4I_I2S_CTRL_GL_EN BIT(0)
#define SUN4I_I2S_FMT0_REG 0x04
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
#define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
#define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
#define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
#define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
#define SUN4I_I2S_FMT1_REG 0x08
#define SUN4I_I2S_FIFO_TX_REG 0x0c
#define SUN4I_I2S_FIFO_RX_REG 0x10
#define SUN4I_I2S_FIFO_CTRL_REG 0x14
#define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
#define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
#define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
#define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
#define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
#define SUN4I_I2S_FIFO_STA_REG 0x18
#define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
#define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
#define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
#define SUN4I_I2S_INT_STA_REG 0x20
#define SUN4I_I2S_CLK_DIV_REG 0x24
#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
#define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
#define SUN4I_I2S_TX_CNT_REG 0x28
#define SUN4I_I2S_RX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
#define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
#define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
#define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
/* Defines required for sun8i-h3 support */
#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
#define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
#define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
#define SUN8I_I2S_INT_STA_REG 0x0c
#define SUN8I_I2S_FIFO_TX_REG 0x20
#define SUN8I_I2S_CHAN_CFG_REG 0x30
#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4)
#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0)
#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
struct sun4i_i2s;
/**
* struct sun4i_i2s_quirks - Differences between SoC variants.
*
* @has_reset: SoC needs reset deasserted.
* @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
* @reg_offset_txdata: offset of the tx fifo.
* @sun4i_i2s_regmap: regmap config to use.
* @field_clkdiv_mclk_en: regmap field to enable mclk output.
* @field_fmt_wss: regmap field to set word select size.
* @field_fmt_sr: regmap field to set sample resolution.
*/
struct sun4i_i2s_quirks {
bool has_reset;
bool has_fmt_set_lrck_period;
unsigned int reg_offset_txdata; /* TX FIFO */
const struct regmap_config *sun4i_i2s_regmap;
/* Register fields for i2s */
struct reg_field field_clkdiv_mclk_en;
struct reg_field field_fmt_wss;
struct reg_field field_fmt_sr;
const struct sun4i_i2s_clk_div *bclk_dividers;
unsigned int num_bclk_dividers;
const struct sun4i_i2s_clk_div *mclk_dividers;
unsigned int num_mclk_dividers;
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*