path: root/sound/soc/stm/stm32_spdifrx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
 *
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>

/* SPDIF-rx Register Map */
#define STM32_SPDIFRX_CR	0x00
#define STM32_SPDIFRX_IMR	0x04
#define STM32_SPDIFRX_SR	0x08
#define STM32_SPDIFRX_IFCR	0x0C
#define STM32_SPDIFRX_DR	0x10
#define STM32_SPDIFRX_CSR	0x14
#define STM32_SPDIFRX_DIR	0x18
#define STM32_SPDIFRX_VERR	0x3F4
#define STM32_SPDIFRX_IDR	0x3F8
#define STM32_SPDIFRX_SIDR	0x3FC

/* Bit definition for SPDIF_CR register */
#define SPDIFRX_CR_SPDIFEN_SHIFT	0
#define SPDIFRX_CR_SPDIFEN_MASK	GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
#define SPDIFRX_CR_SPDIFENSET(x)	((x) << SPDIFRX_CR_SPDIFEN_SHIFT)

#define SPDIFRX_CR_RXDMAEN	BIT(2)
#define SPDIFRX_CR_RXSTEO	BIT(3)

#define SPDIFRX_CR_DRFMT_SHIFT	4
#define SPDIFRX_CR_DRFMT_MASK	GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
#define SPDIFRX_CR_DRFMTSET(x)	((x) << SPDIFRX_CR_DRFMT_SHIFT)

#define SPDIFRX_CR_PMSK		BIT(6)
#define SPDIFRX_CR_VMSK		BIT(7)
#define SPDIFRX_CR_CUMSK	BIT(8)
#define SPDIFRX_CR_PTMSK	BIT(9)
#define SPDIFRX_CR_CBDMAEN	BIT(10)
#define SPDIFRX_CR_CHSEL_SHIFT	11
#define SPDIFRX_CR_CHSEL	BIT(SPDIFRX_CR_CHSEL_SHIFT)

#define SPDIFRX_CR_NBTR_SHIFT	12
#define SPDIFRX_CR_NBTR_MASK	GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
#define SPDIFRX_CR_NBTRSET(x)	((x) << SPDIFRX_CR_NBTR_SHIFT)

#define SPDIFRX_CR_WFA		BIT(14)

#define SPDIFRX_CR_INSEL_SHIFT	16
#define SPDIFRX_CR_INSEL_MASK	GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
#define SPDIFRX_CR_INSELSET(x)	((x) << SPDIFRX_CR_INSEL_SHIFT)

#define SPDIFRX_CR_CKSEN_SHIFT	20
#define SPDIFRX_CR_CKSEN	BIT(20)
#define SPDIFRX_CR_CKSBKPEN	BIT(21)

/* Bit definition for SPDIFRX_IMR register */
#define SPDIFRX_IMR_RXNEI	BIT(0)
#define SPDIFRX_IMR_CSRNEIE	BIT(1)
#define SPDIFRX_IMR_PERRIE	BIT(2)
#define SPDIFRX_IMR_OVRIE	BIT(3)
#define SPDIFRX_IMR_SBLKIE	BIT(4)
#define SPDIFRX_IMR_SYNCDIE	BIT(5)
#define SPDIFRX_IMR_IFEIE	BIT(6)

#define SPDIFRX_XIMR_MASK	GENMASK(6, 0)

/* Bit definition for SPDIFRX_SR register */
#define SPDIFRX_SR_RXNE		BIT(0)
#define SPDIFRX_SR_CSRNE	BIT(1)
#define SPDIFRX_SR_PERR		BIT(2)
#define SPDIFRX_SR_OVR		BIT(3)
#define SPDIFRX_SR_SBD		BIT(4)
#define SPDIFRX_SR_SYNCD	BIT(5)
#define SPDIFRX_SR_FERR		BIT(6)
#define SPDIFRX_SR_SERR		BIT(7)
#define SPDIFRX_SR_TERR		BIT(8)

#define SPDIFRX_SR_WIDTH5_SHIFT	16
#define SPDIFRX_SR_WIDTH5_MASK	GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
#define SPDIFRX_SR_WIDTH5SET(x)	((x) << SPDIFRX_SR_WIDTH5_SHIFT)

/* Bit definition for SPDIFRX_IFCR register */
#define SPDIFRX_IFCR_PERRCF	BIT(2)
#define SPDIFRX_IFCR_OVRCF	BIT(3)
#define SPDIFRX_IFCR_SBDCF	BIT(4)
#define SPDIFRX_IFCR_SYNCDCF	BIT(5)

#define SPDIFRX_XIFCR_MASK	GENMASK(5, 2)

/* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
#define SPDIFRX_DR0_DR_SHIFT	0
#define SPDIFRX_DR0_DR_MASK	GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
#define SPDIFRX_DR0_DRSET(x)	((x) << SPDIFRX_DR0_DR_SHIFT)

#define SPDIFRX_DR0_PE		BIT(24)

#define SPDIFRX_DR0_V		BIT(25)
#define SPDIFRX_DR0_U		BIT(26)
#define SPDIFRX_DR0_C		BIT(27)

#define SPDIFRX_DR0_PT_SHIFT	28
#define SPDIFRX_DR0_PT_MASK	GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
#define SPDIFRX_DR0_PTSET(x)	((x) << SPDIFRX_DR0_PT_SHIFT)

/* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
#define  SPDIFRX_DR1_PE		BIT(0)
#define  SPDIFRX_DR1_V		BIT(1)
#define  SPDIFRX_DR1_U		BIT(2)
#define  SPDIFRX_DR1_C		BIT(3)

#define  SPDIFRX_DR1_PT_SHIFT	4
#define  SPDIFRX_DR1_PT_MASK	GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
#define  SPDIFRX_DR1_PTSET(x)	((x) << SPDIFRX_DR1_PT_SHIFT)

#define SPDIFRX_DR1_DR_SHIFT	8
#define SPDIFRX_DR1_DR_MASK	GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
#define SPDIFRX_DR1_DRSET(x)	((x) << SPDIFRX_DR1_DR_SHIFT)

/* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
#define SPDIFRX_DR1_DRNL1_SHIFT	0
#define SPDIFRX_DR1_DRNL1_MASK	GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
#define SPDIFRX_DR1_DRNL1SET(x)	((x) << SPDIFRX_DR1_DRNL1_SHIFT)

#define SPDIFRX_DR1_DRNL2_SHIFT	16
#define SPDIFRX_DR1_DRNL2_MASK	GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
#define SPDIFRX_DR1_DRNL2SET(x)	((x) << SPDIFRX_DR1_DRNL2_SHIFT)

/* Bit definition for SPDIFRX_CSR register */
#define SPDIFRX_CSR_USR_SHIFT	0
#define SPDIFRX_CSR_USR_MASK	GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
#define SPDIFRX_CSR_USRGET(x)	(((x) & SPDIFRX_CSR_USR_MASK)\
				>> SPDIFRX_CSR_USR_SHIFT)

#define SPDIFRX_CSR_CS_SHIFT	16
#define SPDIFRX_CSR_CS_MASK	GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
#define SPDIFRX_CSR_CSGET(x)	(((x) & SPDIFRX_CSR_CS_MASK)\
				>> SPDIFRX_CSR_CS_SHIFT)

#define SPDIFRX_CSR_SOB		BIT(24)

/* Bit definition for SPDIFRX_DIR register */
#define SPDIFRX_DIR_THI_SHIFT	0
#define SPDIFRX_DIR_THI_MASK	GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
#define SPDIFRX_DIR_THI_SET(x)	((x) << SPDIFRX_DIR_THI_SHIFT)

#define SPDIFRX_DIR_TLO_SHIFT	16
#define SPDIFRX_DIR_TLO_MASK	GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
#define SPDIFRX_DIR_TLO_SET(x)	((x) << SPDIFRX_DIR_TLO_SHIFT)

#define SPDIFRX_SPDIFEN_DISABLE	0x0
#define SPDIFRX_SPDIFEN_SYNC	0x1
#define SPDIFRX_SPDIFEN_ENABLE	0x3

/* Bit definition for SPDIFRX_VERR register */
#define SPDIFRX_VERR_MIN_MASK	GENMASK(3, 0)
#define SPDIFRX_VERR_MAJ_MASK	GENMASK(7, 4)

/* Bit definition for SPDIFRX_IDR register */
#define SPDIFRX_IDR_ID_MASK	GENMASK(31, 0)

/* Bit definition for SPDIFRX_SIDR register */
#define SPDIFRX_SIDR_SID_MASK	GENMASK(31, 0)

#define SPDIFRX_IPIDR_NUMBER	0x00130041

#define SPDIFRX_IN1		0x1
#define SPDIFRX_IN2		0x2
#define SPDIFRX_IN3		0x3
#define SPDIFRX_IN4		0x4
#define SPDIFRX_IN5		0x5
#define SPDIFRX_IN6		0x6
#define SPDIFRX_IN7		0x7
#define SPDIFRX_IN8		0x8

#define SPDIFRX_NBTR_NONE	0x0
#define SPDIFRX_NBTR_3		0x1
#define SPDIFRX_NBTR_15		0x2
#define SPDIFRX_NBTR_63		0x3

#define SPDIFRX_DRFMT_RIGHT	0x0
#define SPDIFRX_DRFMT_LEFT	0x1
#define SPDIFRX_DRFMT_PACKED	0x2

/* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
#define SPDIFRX_CS_BYTES_NB	24
#define SPDIFRX_UB_BYTES_NB	48

/*
 * CSR register is retrieved as a 32 bits word
 * It contains 1 channel status byte and 2 user data bytes
 * 2 S/PDIF frames are acquired to get all CS/UB bits
 */
#define SPDIFRX_CSR_BUF_LENGTH	(SPDIFRX_CS_BYTES_NB * 4 * 2)

/**
 * struct stm32_spdifrx_data - private data of SPDIFRX
 * @pdev: device data pointer
 * @base: mmio register base virtual address
 * @regmap: SPDIFRX register map pointer
 * @regmap_conf: SPDIFRX register map configuration pointer
 * @cs_completion: channel status retrieving completion
 * @kclk: kernel clock feeding the SPDIFRX clock generator
 * @dma_params: dma configuration data for rx channel
 * @substream: PCM substream data pointer
 * @dmab: dma buffer info pointer
 * @ctrl_chan: dma channel for S/PDIF control bits
 * @desc:dma async transaction descriptor
 * @slave_config: dma slave channel runtime config pointer
 * @phys_addr: SPDIFRX registers physical base address
 * @lock: synchronization enabling lock
 * @irq_lock: prevent race condition with IRQ on stream state
 * @cs: channel status buffer
 * @ub: user data buffer
 * @irq: SPDIFRX interrupt line
 * @refcount: keep count of opened DMA channels
 */
struct stm32_spdifrx_data {
	struct platform_device *pdev;
	void __iomem *base;
	struct regmap *regmap;
	const struct regmap_config *regmap_conf;
	struct completion cs_completion;
	struct clk *kclk;
	struct snd_dmaengine_dai_dma_data dma_params;
	struct snd_pcm_substream *substream;
	struct snd_dma_buffer *dmab;
	struct dma_chan *ctrl_chan;
	struct dma_async_tx_descriptor *desc;
	struct dma_slave_config slave_config;
	dma_addr_t phys_addr;
	spinlock_t lock;  /* Sync enabling lock */
	spinlock_t irq_lock; /* Prevent race condition on stream state */
	unsigned char cs[SPDIFRX_CS_BYTES_NB];
	unsigned char ub[SPDIFRX_UB_BYTES_NB];
	int irq;
	int refcount;
};

static void stm32_spdifrx_dma_complete(void *data)
{
	struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
	struct platform_device *pdev = spdifrx->pdev;
	u32 *p_start = (u32 *)spdifrx->dmab->area;
	u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
	u32 *ptr = p_start;
	u16