1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
|
/*
* SiRF USP in I2S/DSP mode
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include "sirf-usp.h"
struct sirf_usp {
struct regmap *regmap;
struct clk *clk;
u32 mode1_reg;
u32 mode2_reg;
int daifmt_format;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct snd_dmaengine_dai_dma_data capture_dma_data;
};
static void sirf_usp_tx_enable(struct sirf_usp *usp)
{
regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
USP_TX_FIFO_RESET, USP_TX_FIFO_RESET);
regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
USP_TX_FIFO_START, USP_TX_FIFO_START);
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
USP_TX_ENA, USP_TX_ENA);
}
static void sirf_usp_tx_disable(struct sirf_usp *usp)
{
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
USP_TX_ENA, ~USP_TX_ENA);
/* FIFO stop */
regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
}
static void sirf_usp_rx_enable(struct sirf_usp *usp)
{
regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
USP_RX_FIFO_RESET, USP_RX_FIFO_RESET);
regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
USP_RX_FIFO_START, USP_RX_FIFO_START);
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
USP_RX_ENA, USP_RX_ENA);
}
static void sirf_usp_rx_disable(struct sirf_usp *usp)
{
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
USP_RX_ENA, ~USP_RX_ENA);
/* FIFO stop */
regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
}
static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai)
{
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data,
&usp->capture_dma_data);
return 0;
}
static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
{
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
break;
default:
dev_err(dai->dev, "Only CBM and CFM supported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_DSP_A:
usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
break;
default:
dev_err(dai->dev, "Only I2S and DSP_A format supported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK);
break;
default:
return -EINVAL;
}
return 0;
}
static void sirf_usp_i2s_init(struct sirf_usp *usp)
{
/* Configure RISC mode */
regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE,
USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL);
/*
* Configure DMA IO Length register
* Set no limit, USP can receive data continuously until it is diabled
*/
regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0);
regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0);
/* Configure Mode2 register */
regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) |
(0 << USP_TXD_DELAY_LEN_OFFSET) |
USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE);
/* Configure Mode1 register */
regmap_write(usp->regmap, USP_MODE1,
USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING |
USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 |
USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE);
/* Configure RX DMA IO Control register */
regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0);
/* Congiure RX FIFO Control register */
regmap_write(usp->regmap, USP_RX_FIFO_CTRL,
(USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) |
(USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET));
/* Congiure RX FIFO Level Check register */
regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK,
RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B));
/* Configure TX DMA IO Control register*/
regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0);
/* Configure TX FIFO Control register */
regmap_write(usp->regmap, USP_TX_FIFO_CTRL,
(USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) |
(USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET));
/* Congiure TX FIFO Level Check register */
regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK,
TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04));
}
static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
u32 data_len, frame_len, shifter_len;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
data_len = 16;
frame_len = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
data_len = 24;
frame_len = 32;
break;
case SNDRV_PCM_FORMAT_S24_3LE:
data_len = 24;
frame_len = 24;
break;
default:
dev_err(dai->dev, "Format unsupported\n");
return -EINVAL;
}
shifter_len = data_len;
switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG);
break;
case SND_SOC_DAIFMT_DSP_A:
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
USP_I2S_SYNC_CHG, 0);
frame_len = data_len * params_channels(params);
data_len = frame_len;
break;
default:
dev_err(dai->dev, "Only support I2S and DSP_A mode\n");
return -EINVAL;
}
switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
regmap_update_bits(usp->regmap, USP_MODE1,
USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING,
USP_RXD_ACT_EDGE_FALLING);
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL,
USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK
| USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE,
((data_len - 1) << USP_TXC_DATA_LEN_OFFSET)
| ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET)
| ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET)
| USP_TXC_SLAVE_CLK_SAMPLE);
else
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK
| USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE,
((data_len - 1) << USP_RXC_DATA_LEN_OFFSET)
| ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET)
| ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET)
| USP_SINGLE_SYNC_MODE);
return 0;
}
static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sirf_usp_tx_enable(usp);
else
sirf_usp_rx_enable(usp);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
sirf_usp_tx_disable(usp);
else
|