// SPDX-License-Identifier: GPL-2.0-only
/*
* skl.c - Implementation of ASoC Intel SKL HD Audio driver
*
* Copyright (C) 2014-2015 Intel Corp
* Author: Jeeja KP <jeeja.kp@intel.com>
*
* Derived mostly from Intel HDA driver with following copyrights:
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
* PeiSen Hou <pshou@realtek.com.tw>
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include <sound/soc-acpi.h>
#include <sound/soc-acpi-intel-match.h>
#include <sound/hda_register.h>
#include <sound/hdaudio.h>
#include <sound/hda_i915.h>
#include <sound/hda_codec.h>
#include "skl.h"
#include "skl-sst-dsp.h"
#include "skl-sst-ipc.h"
#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
#include "../../../soc/codecs/hdac_hda.h"
#endif
static int skl_pci_binding;
module_param_named(pci_binding, skl_pci_binding, int, 0444);
MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
/*
* initialize the PCI registers
*/
static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
unsigned char mask, unsigned char val)
{
unsigned char data;
pci_read_config_byte(pci, reg, &data);
data &= ~mask;
data |= (val & mask);
pci_write_config_byte(pci, reg, data);
}
static void skl_init_pci(struct skl_dev *skl)
{
struct hdac_bus *bus = skl_to_bus(skl);
/*
* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
* TCSEL == Traffic Class Select Register, which sets PCI express QOS
* Ensuring these bits are 0 clears playback static on some HD Audio
* codecs.
* The PCI register TCSEL is defined in the Intel manuals.
*/
dev_dbg(bus->dev, "Clearing TCSEL\n");
skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
}
static void update_pci_dword(struct pci_dev *pci,
unsigned int reg, u32 mask, u32 val)
{
u32 data = 0;
pci_read_config_dword(pci, reg, &data);
data &= ~mask;
data |= (val & mask);
pci_write_config_dword(pci, reg, data);
}
/*
* skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
*
* @dev: device pointer
* @enable: enable/disable flag
*/
static void skl_enable_miscbdcge(struct device *dev, bool enable)
{
struct pci_dev *pci = to_pci_dev(dev);
u32 val;
val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
}
/**
* skl_clock_power_gating: Enable/Disable clock and power gating
*
* @dev: Device pointer
* @enable: Enable/Disable flag
*/
static void skl_clock_power_gating(struct device *dev, bool enable)
{
struct pci_dev *pci = to_pci_dev(dev);
struct hdac_bus *bus = pci_get_drvdata(pci);
u32 val;
/* Update PDCGE bit of CGCTL register */
val = enable ? AZX_CGCTL_ADSPDCGE : 0;
update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
/* Update L1SEN bit of EM2 register */
val =