/*
* skl.c - Implementation of ASoC Intel SKL HD Audio driver
*
* Copyright (C) 2014-2015 Intel Corp
* Author: Jeeja KP <jeeja.kp@intel.com>
*
* Derived mostly from Intel HDA driver with following copyrights:
* Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
* PeiSen Hou <pshou@realtek.com.tw>
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include "../common/sst-acpi.h"
#include <sound/hda_register.h>
#include <sound/hdaudio.h>
#include <sound/hda_i915.h>
#include "skl.h"
#include "skl-sst-dsp.h"
#include "skl-sst-ipc.h"
static struct skl_machine_pdata skl_dmic_data;
/*
* initialize the PCI registers
*/
static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
unsigned char mask, unsigned char val)
{
unsigned char data;
pci_read_config_byte(pci, reg, &data);
data &= ~mask;
data |= (val & mask);
pci_write_config_byte(pci, reg, data);
}
static void skl_init_pci(struct skl *skl)
{
struct hdac_ext_bus *ebus = &skl->ebus;
/*
* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
* TCSEL == Traffic Class Select Register, which sets PCI express QOS
* Ensuring these bits are 0 clears playback static on some HD Audio
* codecs.
* The PCI register TCSEL is defined in the Intel manuals.
*/
dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
}
static void update_pci_dword(struct pci_dev *pci,
unsigned int reg, u32 mask, u32 val)
{
u32 data = 0;
pci_read_config_dword(pci, reg, &data);
data &= ~mask;
data |= (val & mask);
pci_write_config_dword(pci, reg, data);
}
/*
* skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
*
* @dev: device pointer
* @enable: enable/disable flag
*/
static void skl_enable_miscbdcge(struct device *dev, bool enable)
{
struct pci_dev *pci = to_pci_dev(dev);
u32 val;
val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
}
/*
* While performing reset, controller may not come back properly causing
* issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
* (init chip) and then again set CGCTL.MISCBDCGE to 1
*/
static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
{
int ret;
skl_enable_miscbdcge(bus->dev, false);
ret = snd_hdac_bus_init_chip(bus, full_reset);
skl_enable_miscbdcge(bus->dev, true);
return ret;
}
void skl_update_d0i3c(struct device *dev, bool enable)
{
struct pci_dev *pci = to_pci_dev(dev);
struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
struct hdac_bus *bus = ebus_to_hbus(ebus);
u8 reg;
int timeout = 50;
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
/* Do not write to D0I3C until command in progress bit is cleared */
while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
udelay(10);
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
}
/* Highly unlikely. But if it happens, flag error explicitly */
if (!timeout) {
dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
return;
}
if (enable)
reg = reg | AZX_REG_VS_D0I3C_I3;
else
reg = reg & (~AZX_REG_VS_D0I3C_I3);
snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
timeout = 50;
/* Wait for cmd in progress to be cleared before exiting the function */
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
udelay(10);
reg = snd_hdac_chip_readb(bus, VS_D0I3C);
}
/* Highly unlikely. But if it happens, flag error explicitly */
if (!timeout) {
dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
return;
}
dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
snd_hdac_chip_readb(bus, VS_D0I3C));
}
/* called from IRQ */
static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
{
snd_pcm_period_elapsed(hstr->substream);
}
static irqreturn_t skl_interrupt(int irq, void *dev_id)
{
struct hdac_ext_bus