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/*
* CS4271 ASoC codec driver
*
* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This driver support CS4271 codec being master or slave, working
* in control port mode, connected either via SPI or I2C.
* The data format accepted is I2S or left-justified.
* DAPM support not implemented.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/cs4271.h>
#include "cs4271.h"
#define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
#define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000
/*
* CS4271 registers
*/
#define CS4271_MODE1 0x01 /* Mode Control 1 */
#define CS4271_DACCTL 0x02 /* DAC Control */
#define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */
#define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */
#define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */
#define CS4271_ADCCTL 0x06 /* ADC Control */
#define CS4271_MODE2 0x07 /* Mode Control 2 */
#define CS4271_CHIPID 0x08 /* Chip ID */
#define CS4271_FIRSTREG CS4271_MODE1
#define CS4271_LASTREG CS4271_MODE2
#define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
/* Bit masks for the CS4271 registers */
#define CS4271_MODE1_MODE_MASK 0xC0
#define CS4271_MODE1_MODE_1X 0x00
#define CS4271_MODE1_MODE_2X 0x80
#define CS4271_MODE1_MODE_4X 0xC0
#define CS4271_MODE1_DIV_MASK 0x30
#define CS4271_MODE1_DIV_1 0x00
#define CS4271_MODE1_DIV_15 0x10
#define CS4271_MODE1_DIV_2 0x20
#define CS4271_MODE1_DIV_3 0x30
#define CS4271_MODE1_MASTER 0x08
#define CS4271_MODE1_DAC_DIF_MASK 0x07
#define CS4271_MODE1_DAC_DIF_LJ 0x00
#define CS4271_MODE1_DAC_DIF_I2S 0x01
#define CS4271_MODE1_DAC_DIF_RJ16 0x02
#define CS4271_MODE1_DAC_DIF_RJ24 0x03
#define CS4271_MODE1_DAC_DIF_RJ20 0x04
#define CS4271_MODE1_DAC_DIF_RJ18 0x05
#define CS4271_DACCTL_AMUTE 0x80
#define CS4271_DACCTL_IF_SLOW 0x40
#define CS4271_DACCTL_DEM_MASK 0x30
#define CS4271_DACCTL_DEM_DIS 0x00
#define CS4271_DACCTL_DEM_441 0x10
#define CS4271_DACCTL_DEM_48 0x20
#define CS4271_DACCTL_DEM_32 0x30
#define CS4271_DACCTL_SVRU 0x08
#define CS4271_DACCTL_SRD 0x04
#define CS4271_DACCTL_INVA 0x02
#define CS4271_DACCTL_INVB 0x01
#define CS4271_DACVOL_BEQUA 0x40
#define CS4271_DACVOL_SOFT 0x20
#define CS4271_DACVOL_ZEROC 0x10
#define CS4271_DACVOL_ATAPI_MASK 0x0F
#define CS4271_DACVOL_ATAPI_M_M 0x00
#define CS4271_DACVOL_ATAPI_M_BR 0x01
#define CS4271_DACVOL_ATAPI_M_BL 0x02
#define CS4271_DACVOL_ATAPI_M_BLR2 0x03
#define CS4271_DACVOL_ATAPI_AR_M 0x04
#define CS4271_DACVOL_ATAPI_AR_BR 0x05
#define CS4271_DACVOL_ATAPI_AR_BL 0x06
#define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
#define CS4271_DACVOL_ATAPI_AL_M 0x08
#define CS4271_DACVOL_ATAPI_AL_BR 0x09
#define CS4271_DACVOL_ATAPI_AL_BL 0x0A
#define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
#define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
#define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
#define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
#define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
#define CS4271_VOLA_MUTE 0x80
#define CS4271_VOLA_VOL_MASK 0x7F
#define CS4271_VOLB_MUTE 0x80
#define CS4271_VOLB_VOL_MASK 0x7F
#define CS4271_ADCCTL_DITHER16 0x20
#define CS4271_ADCCTL_ADC_DIF_MASK 0x10
#define CS4271_ADCCTL_ADC_DIF_LJ 0x00
#define CS4271_ADCCTL_ADC_DIF_I2S 0x10
#define CS4271_ADCCTL_MUTEA 0x08
#define CS4271_ADCCTL_MUTEB 0x04
#define CS4271_ADCCTL_HPFDA 0x02
#define CS4271_ADCCTL_HPFDB 0x01
#define CS4271_MODE2_LOOP 0x10
#define CS4271_MODE2_MUTECAEQUB 0x08
#define CS4271_MODE2_FREEZE 0x04
#define CS4271_MODE2_CPEN 0x02
#define CS4271_MODE2_PDN 0x01
#define CS4271_CHIPID_PART_MASK 0xF0
#define CS4271_CHIPID_REV_MASK 0x0F
/*
* Default CS4271 power-up configuration
* Array contains non-existing in hw register at address 0
* Array do not include Chip ID, as codec driver does not use
* registers read operations at all
*/
static const struct reg_default cs4271_reg_defaults[] = {
{ CS4271_MODE1, 0, },
{ CS4271_DACCTL, CS4271_DACCTL_AMUTE, },
{ CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, },
{ CS4271_VOLA, 0, },
{ CS4271_VOLB, 0, },
{ CS4271_ADCCTL, 0, },
{ CS4271_MODE2, 0, },
};
static bool cs4271_volatile_reg(struct device *dev, unsigned int reg)
{
return reg == CS4271_CHIPID;
}
static const char * const supply_names[] = {
"vd", "vl", "va"
};
struct cs4271_private {
unsigned int mclk;
bool master;
bool deemph;
struct regmap *regmap;
/* Current sample rate for de-emphasis control */
int rate;
/* GPIO driving Reset pin, if any */
int gpio_nreset;
/* GPIO that disable serial bus, if any */
int gpio_disable;
/* enable soft reset workaround */
bool enable_soft_reset;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AINA"),
SND_SOC_DAPM_INPUT("AINB"),
SND_SOC_DAPM_OUTPUT("AOUTA+"),
SND_SOC_DAPM_OUTPUT("AOUTA-"),
SND_SOC_DAPM_OUTPUT("AOUTB+"),
SND_SOC_DAPM_OUTPUT("AOUTB-"),
};
static const struct snd_soc_dapm_route cs4271_dapm_routes[] = {
{ "Capture", NULL, "AINA" },
{ "Capture", NULL, "AINB" },
{ "AOUTA+", NULL, "Playback" },
{ "AOUTA-", NULL, "Playback" },
{ "AOUTB+", NULL, "Playback" },
{ "AOUTB-", NULL, "Playback" },
};
/*
* @freq is the desired MCLK rate
* MCLK rate should (c) be the sample rate, multiplied by one of the
* ratios listed in cs4271_mclk_fs_ratios table
*/
static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
cs4271->mclk = freq;
return 0;
}
static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_component *component = codec_dai->component;
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
unsigned int val = 0;
int ret;
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs4271->master = false;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs4271->master = true;
val |= CS4271_MODE1_MASTER;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
val |= CS4271_MODE1_DAC_DIF_LJ;
ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ);
if (ret < 0)
return ret;
break;
case SND_SOC_DAIFMT_I2S:
val |= CS4271_MODE1_DAC_DIF_I2S;
ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL,
CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S);
if (ret < 0)
return ret;
break;
default:
dev_err(component->dev, "Invalid DAI format\n");
return -EINVAL;
}
ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1,
CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val);
if (ret < 0)
return ret;
return 0;
}
static int cs4271_deemph[] = {0, 44100, 48000, 32000};
static int cs4271_set_deemph(struct snd_soc_component *component)
{
struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component);
int i, ret;
int val = CS4271_DACCTL_DEM_DIS;
if (cs4271->deemph) {
/* Find closest de-emphasis freq */
val = 1;
for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++)
if (abs(cs4271_deemph[i] - cs4271->rate) <
abs(cs4271_deemph[val
|