/*
* cs35l34.c -- CS35l34 ALSA SoC audio driver
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <Paul.Handrigan@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/pm_runtime.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs35l34.h>
#include "cs35l34.h"
#define PDN_DONE_ATTEMPTS 10
#define CS35L34_START_DELAY 50
struct cs35l34_private {
struct snd_soc_component *component;
struct cs35l34_platform_data pdata;
struct regmap *regmap;
struct regulator_bulk_data core_supplies[2];
int num_core_supplies;
int mclk_int;
bool tdm_mode;
struct gpio_desc *reset_gpio; /* Active-low reset GPIO */
};
static const struct reg_default cs35l34_reg[] = {
{CS35L34_PWRCTL1, 0x01},
{CS35L34_PWRCTL2, 0x19},
{CS35L34_PWRCTL3, 0x01},
{CS35L34_ADSP_CLK_CTL, 0x08},
{CS35L34_MCLK_CTL, 0x11},
{CS35L34_AMP_INP_DRV_CTL, 0x01},
{CS35L34_AMP_DIG_VOL_CTL, 0x12},
{CS35L34_AMP_DIG_VOL, 0x00},
{CS35L34_AMP_ANLG_GAIN_CTL, 0x0F},
{CS35L34_PROTECT_CTL, 0x06},
{CS35L34_AMP_KEEP_ALIVE_CTL, 0x04},
{CS35L34_BST_CVTR_V_CTL, 0x00},
{CS35L34_BST_PEAK_I, 0x10},
{CS35L34_BST_RAMP_CTL, 0x87},
{CS35L34_BST_CONV_COEF_1, 0x24},
{CS35L34_BST_CONV_COEF_2, 0x24},
{CS35L34_BST_CONV_SLOPE_COMP, 0x4E},
{CS35L34_BST_CONV_SW_FREQ, 0x08},
{CS35L34_CLASS_H_CTL, 0x0D},
{CS35L34_CLASS_H_HEADRM_CTL, 0x0D},
{CS35L34_CLASS_H_RELEASE_RATE, 0x08},
{CS35L34_CLASS_H_FET_DRIVE_CTL, 0x41},
{CS35L34_CLASS_H_STATUS, 0x05},
{CS35L34_VPBR_CTL, 0x0A},
{CS35L34_VPBR_VOL_CTL, 0x90},
{CS35L34_VPBR_TIMING_CTL, 0x6A},
{CS35L34_PRED_MAX_ATTEN_SPK_LOAD, 0x95},
{CS35L34_PRED_BROWNOUT_THRESH, 0x1C},
{CS35L34_PRED_BROWNOUT_VOL_CTL, 0x00},
{CS35L34_PRED_BROWNOUT_RATE_CTL, 0x10},
{CS35L34_PRED_WAIT_CTL, 0x10},
{CS35L34_PRED_ZVP_INIT_IMP_CTL, 0x08},
{CS35L34_PRED_MAN_SAFE_VPI_CTL, 0x80},
{CS35L34_VPBR_ATTEN_STATUS, 0x00},
{CS35L34_PRED_BRWNOUT_ATT_STATUS, 0x00},
{CS35L34_SPKR_MON_CTL, 0xC6},
{CS35L34_ADSP_I2S_CTL, 0x00},
{CS35L34_ADSP_TDM_CTL, 0x00},
{CS35L34_TDM_TX_CTL_1_VMON, 0x00},
{CS35L34_TDM_TX_CTL_2_IMON, 0x04},
{CS35L34_TDM_TX_CTL_3_VPMON, 0x03},
{CS35L34_TDM_TX_CTL_4_VBSTMON, 0x07},
{CS35L34_TDM_TX_CTL_5_FLAG1, 0x08},
{CS35L34_TDM_TX_CTL_6_FLAG2, 0x09},
{CS35L34_TDM_TX_SLOT_EN_1