path: root/sound/soc/atmel/atmel-i2s.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Atmel I2S controller
 *
 * Copyright (C) 2015 Atmel Corporation
 *
 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>

#define ATMEL_I2SC_MAX_TDM_CHANNELS	8

/*
 * ---- I2S Controller Register map ----
 */
#define ATMEL_I2SC_CR		0x0000	/* Control Register */
#define ATMEL_I2SC_MR		0x0004	/* Mode Register */
#define ATMEL_I2SC_SR		0x0008	/* Status Register */
#define ATMEL_I2SC_SCR		0x000c	/* Status Clear Register */
#define ATMEL_I2SC_SSR		0x0010	/* Status Set Register */
#define ATMEL_I2SC_IER		0x0014	/* Interrupt Enable Register */
#define ATMEL_I2SC_IDR		0x0018	/* Interrupt Disable Register */
#define ATMEL_I2SC_IMR		0x001c	/* Interrupt Mask Register */
#define ATMEL_I2SC_RHR		0x0020	/* Receiver Holding Register */
#define ATMEL_I2SC_THR		0x0024	/* Transmitter Holding Register */
#define ATMEL_I2SC_VERSION	0x0028	/* Version Register */

/*
 * ---- Control Register (Write-only) ----
 */
#define ATMEL_I2SC_CR_RXEN	BIT(0)	/* Receiver Enable */
#define ATMEL_I2SC_CR_RXDIS	BIT(1)	/* Receiver Disable */
#define ATMEL_I2SC_CR_CKEN	BIT(2)	/* Clock Enable */
#define ATMEL_I2SC_CR_CKDIS	BIT(3)	/* Clock Disable */
#define ATMEL_I2SC_CR_TXEN	BIT(4)	/* Transmitter Enable */
#define ATMEL_I2SC_CR_TXDIS	BIT(5)	/* Transmitter Disable */
#define ATMEL_I2SC_CR_SWRST	BIT(7)	/* Software Reset */

/*
 * ---- Mode Register (Read/Write) ----
 */
#define ATMEL_I2SC_MR_MODE_MASK		GENMASK(0, 0)
#define ATMEL_I2SC_MR_MODE_SLAVE	(0 << 0)
#define ATMEL_I2SC_MR_MODE_MASTER	(1 << 0)

#define ATMEL_I2SC_MR_DATALENGTH_MASK		GENMASK(4, 2)
#define ATMEL_I2SC_MR_DATALENGTH_32_BITS	(0 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_24_BITS	(1 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_20_BITS	(2 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_18_BITS	(3 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_16_BITS	(4 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT	(5 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_8_BITS		(6 << 2)
#define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT	(7 << 2)

#define ATMEL_I2SC_MR_FORMAT_MASK	GENMASK(7, 6)
#define ATMEL_I2SC_MR_FORMAT_I2S	(0 << 6)
#define ATMEL_I2SC_MR_FORMAT_LJ		(1 << 6)  /* Left Justified */
#define ATMEL_I2SC_MR_FORMAT_TDM	(2 << 6)
#define ATMEL_I2SC_MR_FORMAT_TDMLJ	(3 << 6)

/* Left audio samples duplicated to right audio channel */
#define ATMEL_I2SC_MR_RXMONO		BIT(8)

/* Receiver uses one DMA channel ... */
#define ATMEL_I2SC_MR_RXDMA_MASK	GENMASK(9, 9)
#define ATMEL_I2SC_MR_RXDMA_SINGLE	(0 << 9)  /* for all audio channels */
#define ATMEL_I2SC_MR_RXDMA_MULTIPLE	(1 << 9)  /* per audio channel */

/* I2SDO output of I2SC is internally connected to I2SDI input */
#define ATMEL_I2SC_MR_RXLOOP		BIT(10)

/* Left audio samples duplicated to right audio channel */
#define ATMEL_I2SC_MR_TXMONO		BIT(12)

/* Transmitter uses one DMA channel ... */
#define ATMEL_I2SC_MR_TXDMA_MASK	GENMASK(13, 13)
#define ATMEL_I2SC_MR_TXDMA_SINGLE	(0 << 13)  /* for all audio channels */
#define ATMEL_I2SC_MR_TXDME_MULTIPLE	(1 << 13)  /* per audio channel */

/* x sample transmitted when underrun */
#define ATMEL_I2SC_MR_TXSAME_MASK	GENMASK(14, 14)
#define ATMEL_I2SC_MR_TXSAME_ZERO	(0 << 14)  /* Zero sample */
#define ATMEL_I2SC_MR_TXSAME_PREVIOUS	(1 << 14)  /* Previous sample */

/* Audio Clock to I2SC Master Clock ratio */
#define ATMEL_I2SC_MR_IMCKDIV_MASK	GENMASK(21, 16)
#define ATMEL_I2SC_MR_IMCKDIV(div) \
	(((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)

/* Master Clock to fs ratio */
#define ATMEL_I2SC_MR_IMCKFS_MASK	GENMASK(29, 24)
#define ATMEL_I2SC_MR_IMCKFS(fs) \
	(((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)

/* Master Clock mode */
#define ATMEL_I2SC_MR_IMCKMODE_MASK	GENMASK(30, 30)
/* 0: No master clock generated (selected clock drives I2SCK pin) */
#define ATMEL_I2SC_MR_IMCKMODE_I2SCK	(0 << 30)
/* 1: master clock generated (internally generated clock drives I2SMCK pin) */
#define ATMEL_I2SC_MR_IMCKMODE_I2SMCK	(1 << 30)

/* Slot Width */
/* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
/* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
#define ATMEL_I2SC_MR_IWS		BIT(31)

/*
 * ---- Status Registers ----
 */
#define ATMEL_I2SC_SR_RXEN	BIT(0)	/* Receiver Enabled */
#define ATMEL_I2SC_SR_RXRDY	BIT(1)	/* Receive Ready */
#define ATMEL_I2SC_SR_RXOR	BIT(2)	/* Receive Overrun */

#define ATMEL_I2SC_SR_TXEN	BIT(4)	/* Transmitter Enabled */
#define ATMEL_I2SC_SR_TXRDY	BIT(5)	/* Transmit Ready */
#define ATMEL_I2SC_SR_TXUR	BIT(6)	/* Transmit Underrun */

/* Receive Overrun Channel */
#define ATMEL_I2SC_SR_RXORCH_MASK	GENMASK(15, 8)
#define ATMEL_I2SC_SR_RXORCH(ch)	(1 << (((ch) & 0x7) + 8))

/* Transmit Underrun Channel */
#define ATMEL_I2SC_SR_TXURCH_MASK	GENMASK(27, 20)
#define ATMEL_I2SC_SR_TXURCH(ch)	(1 << (((ch) & 0x7) + 20))

/*
 * ---- Interrupt Enable/Disable/Mask Registers ----
 */
#define ATMEL_I2SC_INT_RXRDY	ATMEL_I2SC_SR_RXRDY
#define ATMEL_I2SC_INT_RXOR	ATMEL_I2SC_SR_RXOR
#define ATMEL_I2SC_INT_TXRDY	ATMEL_I2SC_SR_TXRDY
#define ATMEL_I2SC_INT_TXUR	ATMEL_I2SC_SR_TXUR

static const struct regmap_config atmel_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = ATMEL_I2SC_VERSION,
};

struct atmel_i2s_gck_param {
	int		fs;
	unsigned long	mck;
	int		imckdiv;
	int		imckfs;
};

#define I2S_MCK_12M288		12288000UL
#define I2S_MCK_11M2896		11289600UL

/* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
static const struct atmel_i2s_gck_param gck_params[] = {
	/* mck = 12.288MHz */
	{  8000, I2S_MCK_12M288, 0, 47},	/* mck = 1536 fs */
	{ 16000, I2S_MCK_12M288, 1, 47},	/* mck =  768 fs */
	{ 24000, I2S_MCK_12M288, 3, 63},	/* mck =  512 fs */
	{ 32000, I2S_MCK_12M288, 3, 47},	/* mck =  384 fs */
	{ 48000, I2S_MCK_12M288, 7, 63},	/* mck =  256 fs */
	{ 64000, I2S_MCK_12M288, 7, 47},	/* mck =  192 fs */
	{ 96000, I2S_MCK_12M288, 7, 31},	/* mck =  128 fs */
	{192000, I2S_MCK_12M288, 7, 15},	/* mck =   64 fs */

	/* mck = 11.2896MHz */
	{ 11025, I2S_MCK_11M2896, 1, 63},	/* mck = 1024 fs */
	{ 22050, I2S_MCK_11M2896, 3, 63},	/* mck =  512 fs */
	{ 44100, I2S_MCK_11M2896, 7, 63},	/* mck =  256 fs */
	{ 88200, I2S_MCK_11M2896, 7, 31},	/* mck =  128 fs */
	{176400, I2S_MCK_11M2896, 7, 15},	/* mck =   64 fs */
};

struct atmel_i2s_dev;

struct atmel_i2s_caps {
	int	(*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
};

struct atmel_i2s_dev {
	struct device				*dev;
	struct regmap				*regmap;
	struct clk				*pclk;
	struct clk				*gclk;
	struct snd_dmaengine_dai_dma_data	playback;
	struct snd_dmaengine_dai_dma_data	capture;
	unsigned int				fmt;
	const struct atmel_i2s_gck_param	*gck_param;
	const struct atmel_i2s_caps		*caps;
};

static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
{
	struct atmel_i2s_dev *dev = dev_id;
	unsigned int sr, imr, pending, ch, mask;
	irqreturn_t ret = IRQ_NONE;

	regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
	regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
	pending = sr & imr;

	if (!pending)
		return IRQ_NONE;

	if (pending & ATMEL_I2SC_INT_RXOR) {
		mask = ATMEL_I2SC_SR_RXOR;

		for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
			if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
				mask |= ATMEL_I2SC_SR_RXORCH(ch);
				dev_err(dev->dev,
					"RX overrun on channel %d\n", ch);
			}
		}
		regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
		ret = IRQ_HANDLED;
	}

	if (pending & ATMEL_I2SC_INT_TXUR) {
		mask = ATMEL_I2SC_SR_TXUR;

		for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
			if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
				mask |= ATMEL_I2SC_SR_TXURCH(ch);
				dev_err(dev->dev,
					"TX underrun on channel %d\n", ch);
			}
		}
		regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
		ret = IRQ_HANDLED;
	}

	return ret;
}

#define ATMEL_I2S_RATES		SNDRV_PCM_RATE_8000_192000

#define ATMEL_I2S_FORMATS	(SNDRV_PCM_FMTBIT_S8 |		\
				 SNDRV_PCM_FMTBIT_S16_LE |	\
				 SNDRV_PCM_FMTBIT_S18_3LE |	\
				 SNDRV_PCM_FMTBIT_S20_3LE |	\
				 SNDRV_PCM_FMTBIT_S24_3LE |	\
				 SNDRV_PCM_FMTBIT_S24_LE |	\
				 SNDRV_PCM_FMTBIT_S32_LE)

static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	dev->fmt = fmt;
	return 0;
}

static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
			     struct snd_soc_dai *dai)
{
	struct atmel_i2s_dev