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|
/*
* bt87x.c - Brooktree Bt878/Bt879 driver for ALSA
*
* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
*
* based on btaudio.c by Gerd Knorr <kraxel@bytesex.org>
*
*
* This driver is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This driver is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <sound/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/control.h>
#include <sound/initval.h>
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_DESCRIPTION("Brooktree Bt87x audio driver");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Brooktree,Bt878},"
"{Brooktree,Bt879}}");
static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
static int digital_rate[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* digital input rate */
static int load_all; /* allow to load the non-whitelisted cards */
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for Bt87x soundcard");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for Bt87x soundcard");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Bt87x soundcard");
module_param_array(digital_rate, int, NULL, 0444);
MODULE_PARM_DESC(digital_rate, "Digital input rate for Bt87x soundcard");
module_param(load_all, bool, 0444);
MODULE_PARM_DESC(load_all, "Allow to load the non-whitelisted cards");
/* register offsets */
#define REG_INT_STAT 0x100 /* interrupt status */
#define REG_INT_MASK 0x104 /* interrupt mask */
#define REG_GPIO_DMA_CTL 0x10c /* audio control */
#define REG_PACKET_LEN 0x110 /* audio packet lengths */
#define REG_RISC_STRT_ADD 0x114 /* RISC program start address */
#define REG_RISC_COUNT 0x120 /* RISC program counter */
/* interrupt bits */
#define INT_OFLOW (1 << 3) /* audio A/D overflow */
#define INT_RISCI (1 << 11) /* RISC instruction IRQ bit set */
#define INT_FBUS (1 << 12) /* FIFO overrun due to bus access latency */
#define INT_FTRGT (1 << 13) /* FIFO overrun due to target latency */
#define INT_FDSR (1 << 14) /* FIFO data stream resynchronization */
#define INT_PPERR (1 << 15) /* PCI parity error */
#define INT_RIPERR (1 << 16) /* RISC instruction parity error */
#define INT_PABORT (1 << 17) /* PCI master or target abort */
#define INT_OCERR (1 << 18) /* invalid opcode */
#define INT_SCERR (1 << 19) /* sync counter overflow */
#define INT_RISC_EN (1 << 27) /* DMA controller running */
#define INT_RISCS_SHIFT 28 /* RISC status bits */
/* audio control bits */
#define CTL_FIFO_ENABLE (1 << 0) /* enable audio data FIFO */
#define CTL_RISC_ENABLE (1 << 1) /* enable audio DMA controller */
#define CTL_PKTP_4 (0 << 2) /* packet mode FIFO trigger point - 4 DWORDs */
#define CTL_PKTP_8 (1 << 2) /* 8 DWORDs */
#define CTL_PKTP_16 (2 << 2) /* 16 DWORDs */
#define CTL_ACAP_EN (1 << 4) /* enable audio capture */
#define CTL_DA_APP (1 << 5) /* GPIO input */
#define CTL_DA_IOM_AFE (0 << 6) /* audio A/D input */
#define CTL_DA_IOM_DA (1 << 6) /* digital audio input */
#define CTL_DA_SDR_SHIFT 8 /* DDF first stage decimation rate */
#define CTL_DA_SDR_MASK (0xf<< 8)
#define CTL_DA_LMT (1 << 12) /* limit audio data values */
#define CTL_DA_ES2 (1 << 13) /* enable DDF stage 2 */
#define CTL_DA_SBR (1 << 14) /* samples rounded to 8 bits */
#define CTL_DA_DPM (1 << 15) /* data packet mode */
#define CTL_DA_LRD_SHIFT 16 /* ALRCK delay */
#define CTL_DA_MLB (1 << 21) /* MSB/LSB format */
#define CTL_DA_LRI (1 << 22) /* left/right indication */
#define CTL_DA_SCE (1 << 23) /* sample clock edge */
#define CTL_A_SEL_STV (0 << 24) /* TV tuner audio input */
#define CTL_A_SEL_SFM (1 << 24) /* FM audio input */
#define CTL_A_SEL_SML (2 << 24) /* mic/line audio input */
#define CTL_A_SEL_SMXC (3 << 24) /* MUX bypass */
#define CTL_A_SEL_SHIFT 24
#define CTL_A_SEL_MASK (3 << 24)
#define CTL_A_PWRDN (1 << 26) /* analog audio power-down */
#define CTL_A_G2X (1 << 27) /* audio gain boost */
#define CTL_A_GAIN_SHIFT 28 /* audio input gain */
#define CTL_A_GAIN_MASK (0xf<<28)
/* RISC instruction opcodes */
#define RISC_WRITE (0x1 << 28) /* write FIFO data to memory at address */
#define RISC_WRITEC (0x5 << 28) /* write FIFO data to memory at current address */
#define RISC_SKIP (0x2 << 28) /* skip FIFO data */
#define RISC_JUMP (0x7 << 28) /* jump to address */
#define RISC_SYNC (0x8 << 28) /* synchronize with FIFO */
/* RISC instruction bits */
#define RISC_BYTES_ENABLE (0xf << 12) /* byte enable bits */
#define RISC_RESYNC ( 1 << 15) /* disable FDSR errors */
#define RISC_SET_STATUS_SHIFT 16 /* set status bits */
#define RISC_RESET_STATUS_SHIFT 20 /* clear status bits */
#define RISC_IRQ ( 1 << 24) /* interrupt */
#define RISC_EOL ( 1 << 26) /* end of line */
#define RISC_SOL ( 1 << 27) /* start of line */
/* SYNC status bits values */
#define RISC_SYNC_FM1 0x6
#define RISC_SYNC_VRO 0xc
#define ANALOG_CLOCK 1792000
#ifdef CONFIG_SND_BT87X_OVERCLOCK
#define CLOCK_DIV_MIN 1
#else
#define CLOCK_DIV_MIN 4
#endif
#define CLOCK_DIV_MAX 15
#define ERROR_INTERRUPTS (INT_FBUS | INT_FTRGT | INT_PPERR | \
INT_RIPERR | INT_PABORT | INT_OCERR)
#define MY_INTERRUPTS (INT_RISCI | ERROR_INTERRUPTS)
/* SYNC, one WRITE per line, one extra WRITE per page boundary, SYNC, JUMP */
#define MAX_RISC_SIZE ((1 + 255 + (PAGE_ALIGN(255 * 4092) / PAGE_SIZE - 1) + 1 + 1) * 8)
typedef struct snd_bt87x bt87x_t;
struct snd_bt87x {
snd_card_t *card;
struct pci_dev *pci;
void __iomem *mmio;
int irq;
int dig_rate;
spinlock_t reg_lock;
long opened;
snd_pcm_substream_t *substream;
struct snd_dma_buffer dma_risc;
unsigned int line_bytes;
unsigned int lines;
u32 reg_control;
u32 interrupt_mask;
int current_line;
int pci_parity_errors;
};
enum { DEVICE_DIGITAL, DEVICE_ANALOG };
static inline u32 snd_bt87x_readl(bt87x_t *chip, u32 reg)
{
return readl(chip->mmio + reg);
}
static inline void snd_bt87x_writel(bt87x_t *chip, u32 reg, u32 value)
{
writel(value, chip->mmio + reg);
}
static int snd_bt87x_create_risc(bt87x_t *chip, snd_pcm_substream_t *substream,
unsigned int periods, unsigned int period_bytes)
{
struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
unsigned int i, offset;
u32 *risc;
if (chip->dma_risc.area == NULL) {
if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
PAGE_ALIGN(MAX_RISC_SIZE), &chip->dma_risc) < 0)
return -ENOMEM;
}
risc = (u32 *)chip->dma_risc.area;
offset = 0;
*risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_FM1);
*risc++ = cpu_to_le32
|