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#ifdef __KERNEL__
#ifndef _PPC_IO_H
#define _PPC_IO_H
#include <linux/config.h>
#include <linux/string.h>
#include <linux/types.h>
#include <asm/page.h>
#include <asm/byteorder.h>
#include <asm/mmu.h>
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
#define SLOW_DOWN_IO
#define PMAC_ISA_MEM_BASE 0
#define PMAC_PCI_DRAM_OFFSET 0
#define CHRP_ISA_IO_BASE 0xf8000000
#define CHRP_ISA_MEM_BASE 0xf7000000
#define CHRP_PCI_DRAM_OFFSET 0
#define PREP_ISA_IO_BASE 0x80000000
#define PREP_ISA_MEM_BASE 0xc0000000
#define PREP_PCI_DRAM_OFFSET 0x80000000
#if defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#elif defined(CONFIG_8xx)
#include <asm/mpc8xx.h>
#elif defined(CONFIG_8260)
#include <asm/mpc8260.h>
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
#elif defined(CONFIG_APUS)
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#else /* Everyone else */
#define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base
#define PCI_DRAM_OFFSET pci_dram_offset
#endif /* Platform-dependent I/O */
#define ___IO_BASE ((void __iomem *)_IO_BASE)
extern unsigned long isa_io_base;
extern unsigned long isa_mem_base;
extern unsigned long pci_dram_offset;
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
int ret;
__asm__ __volatile__(
"lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline int in_le16(const volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline int in_be16(const volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
#if defined (CONFIG_8260_PCI9)
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#else
static inline __u8 readb(const volatile void __iomem *addr)
{
return in_8(addr);
}
static inline void writeb(__u8 b, volatile void __iomem *addr)
{
out_8(addr, b);
}
#endif
#if defined(CONFIG_APUS)
static inline __u16 readw(const volatile void __iomem *addr)
{
return *(__force volatile __u16 *)(addr);
}
static inline __u32 readl(const volatile void __iomem *addr)
{
return *(__force volatile __u32 *)(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
*(__force volatile __u16 *)(addr) = b;
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
*(__force volatile __u32 *)(addr) = b;
}
#elif defined (CONFIG_8260_PCI9)
/* Use macros if PCI9 workaround enabled */
#define readw(addr) in_le16((volatile u16 *)(addr))
#define readl(addr) in_le32((volatile u32 *)(addr))
#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
#else
static inline __u16 readw(const volatile void __iomem *addr)
{
return in_le16(addr);
}
static inline __u32 readl(const volatile void __iomem *addr)
{
return in_le32(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
out_le16(addr, b);
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
out_le32(addr, b);
}
#endif /* CONFIG_APUS */
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
static inline __u8 __raw_readb(const volatile void __iomem *addr)
{
return *(__force volatile __u8 *)(addr);
}
static inline __u16 __raw_readw(const volatile void __iomem *addr)
{
return *(__force volatile __u16 *)(addr);
}
static inline __u32 __raw_readl(const volatile void __iomem *addr)
{
return *(__force volatile __u32 *)(addr);
}
static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
{
*(__force volatile __u8 *)(addr) = b;
}
static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
{
*(__force volatile __u16 *)(addr) = b;
}
static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
{
*(__force volatile __u32 *)(addr) = b;
}
#define mmiowb()
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
/*
* On powermacs, we will get a machine check exception if we
* try to read data from a non-existent I/O port. Because the
* machine check is an asynchronous exception, it isn't
* well-defined which instruction SRR0 will point to when the
* exception occurs.
* With the sequence below (twi; isync; nop), we have found that
* the machine check occurs on one of the three instructions on
* all PPC implementations tested so far. The twi and isync are
* needed on the 601 (in fact twi; sync works too), the isync and
* nop are needed on 604[e|r], and any of twi, sync or isync will
* work on 603[e], 750, 74xx.
* The twi creates an explicit data dependency on the returned
* value which seems to be needed to make the 601 wait for the
* load to finish.
*/
#define __do_in_asm(name, op) \
extern __inline__ unsigned int name(unsigned int port) \
{ \
unsigned int x; \
__asm__
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