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/************************************************************************
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
************************************************************************/
/*
* File: include/asm-blackfin/mach-bf533/defBF532.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
#ifndef _DEF_BF532_H
#define _DEF_BF532_H
/* include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID Register */
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
#define RTC_STAT 0xFFC00300 /* RTC Status Register */
#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
/*
* Because include/linux/serial_reg.h have defined UART_*,
* So we define blackfin uart regs to BFIN_UART_*.
*/
#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
#if 0
#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
#endif
#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */
#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
#define FIO_MASKB_S
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