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/*
* Octeon Watchdog driver
*
* Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
*
* Some parts derived from wdt.c
*
* (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
* warranty for any of this software. This material is provided
* "AS-IS" and at no charge.
*
* (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*
* The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
* For most systems this is less than 10 seconds, so to allow for
* software to request longer watchdog heartbeats, we maintain software
* counters to count multiples of the base rate. If the system locks
* up in such a manner that we can not run the software counters, the
* only result is a watchdog reset sooner than was requested. But
* that is OK, because in this case userspace would likely not be able
* to do anything anyhow.
*
* The hardware watchdog interval we call the period. The OCTEON
* watchdog goes through several stages, after the first period an
* irq is asserted, then if it is not reset, after the next period NMI
* is asserted, then after an additional period a chip wide soft reset.
* So for the software counters, we reset watchdog after each period
* and decrement the counter. But for the last two periods we need to
* let the watchdog progress to the NMI stage so we disable the irq
* and let it proceed. Once in the NMI, we print the register state
* to the serial port and then wait for the reset.
*
* A watchdog is maintained for each CPU in the system, that way if
* one CPU suffers a lockup, we also get a register dump and reset.
* The userspace ping resets the watchdog on all CPUs.
*
* Before userspace opens the watchdog device, we still run the
* watchdogs to catch any lockups that may be kernel related.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/watchdog.h>
#include <linux/cpumask.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/fs.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/uasm.h>
#include <asm/octeon/octeon.h>
/* The count needed to achieve timeout_sec. */
static unsigned int timeout_cnt;
/* The maximum period supported. */
static unsigned int max_timeout_sec;
/* The current period. */
static unsigned int timeout_sec;
/* Set to non-zero when userspace countdown mode active */
static int do_coundown;
static unsigned int countdown_reset;
static unsigned int per_cpu_countdown[NR_CPUS];
static cpumask_t irq_enabled_cpus;
#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
static int heartbeat = WD_TIMO;
module_param(heartbeat, int, S_IRUGO);
MODULE_PARM_DESC(heartbeat,
"Watchdog heartbeat in seconds. (0 < heartbeat, default="
__MODULE_STRING(WD_TIMO) ")");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, S_IRUGO);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static unsigned long octeon_wdt_is_open;
static char expect_close;
static u32 __initdata nmi_stage1_insns[64];
/* We need one branch and therefore one relocation per target label. */
static struct uasm_label __initdata labels[5];
static struct uasm_reloc __initdata relocs[5];
enum lable_id {
label_enter_bootloader = 1
};
/* Some CP0 registers */
#define K0 26
#define C0_CVMMEMCTL 11, 7
#define C0_STATUS 12, 0
#define C0_EBASE 15, 1
#define C0_DESAVE 31, 0
void octeon_wdt_nmi_stage2(void);
static void __init octeon_wdt_build_stage1(void)
{
int i;
int len;
u32 *p = nmi_stage1_insns;
#ifdef CONFIG_HOTPLUG_CPU
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
#endif
/*
* For the next few instructions running the debugger may
* cause corruption of k0 in the saved registers. Since we're
* about to crash, nobody probably cares.
*
* Save K0 into the debug scratch register
*/
uasm_i_dmtc0(&p, K0, C0_DESAVE);
uasm_i_mfc0(&p, K0, C0_STATUS);
#ifdef CONFIG_HOTPLUG_CPU
if (octeon_bootloader_entry_addr)
uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
label_enter_bootloader);
#endif
/* Force 64-bit addressing enabled */
uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
uasm_i_mtc0(&p, K0, C0_STATUS);
#ifdef CONFIG_HOTPLUG_CPU
if (octeon_bootloader_entry_addr) {
uasm_i_mfc0(&p, K0, C0_EBASE);
/* Coreid number in K0 */
uasm_i_andi(&p, K0, K0, 0xf);
/* 8 * coreid in bits 16-31 */
uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
uasm_i_ori(&p, K0, K0, 0x8001);
uasm_i_dsll_safe(&p, K0, K0, 16);
uasm_i_ori(&p, K0, K0, 0x0700);
uasm_i_drotr_safe(&p, K0, K0, 32);
/*
* Should result in: 0x8001,0700,0000,8*coreid which is
* CVMX_CIU_WDOGX(coreid) - 0x0500
*
* Now ld K0, CVMX_CIU_WDOGX(coreid)
*/
uasm_i_ld(&p, K0, 0x500, K0);
/*
* If bit one set handle the NMI as a watchdog event.
* otherwise transfer control to bootloader.
*/
uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
uasm_i_nop(&p);
}
#endif
/* Clear Dcache so cvmseg works right. */
uasm_i_cache(&p, 1, 0, 0);
/* Use K0 to do a read/modify/write of CVMMEMCTL */
uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
/* Clear out the size of CVMSEG */
uasm_i_dins(&p, K0, 0, 0, 6);
/* Set CVMSEG to its largest value */
uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
/* Store the CVMMEMCTL value */
uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
/* Load the address of the second stage handler */
UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
uasm_i_jr(&p, K0);
uasm_i_dmfc0(&p, K0, C0_DESAVE);
#ifdef CONFIG_HOTPLUG_CPU
if (octeon_bootloader_entry_addr) {
uasm_build_label(&l, p, label_enter_bootloader);
/* Jump to the bootloader and restore K0 */
UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
uasm_i_jr(&p, K0);
uasm_i_dmfc0(&p, K0, C0_DESAVE);
}
#endif
uasm_resolve_relocs(relocs, labels);
len = (int)(p - nmi_stage1_insns);
pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
pr_debug("\t.set push\n");
pr_debug("\t.set noreorder\n");
for (i = 0; i < len; i++)
pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
pr_debug("\t.set pop\n");
if (len > 32)
panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", len);
}
static int cpu2core(int cpu)
{
#ifdef CONFIG_SMP
return cpu_logical_map(cpu);
#else
return cvmx_get_core_num();
#endif
}
static int core2cpu(int coreid)
{
#ifdef CONFIG_SMP
return cpu_number_map(coreid);
#else
return 0;
#endif
}
/**
* Poke the watchdog when an interrupt is received
*
* @cpl:
* @dev_id:
*
* Returns
*/
static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
{
unsigned int core =
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