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/*
* linux/drivers/video/w100fb.h
*
* Frame Buffer Device for ATI w100 (Wallaby)
*
* Copyright (C) 2002, ATI Corp.
* Copyright (C) 2004-2005 Richard Purdie
* Copyright (c) 2005 Ian Molton <spyro@f2s.com>
*
* Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
*
* w32xx support by Ian Molton
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#if !defined (_W100FB_H)
#define _W100FB_H
/* Block CIF Start: */
#define mmCHIP_ID 0x0000
#define mmREVISION_ID 0x0004
#define mmWRAP_BUF_A 0x0008
#define mmWRAP_BUF_B 0x000C
#define mmWRAP_TOP_DIR 0x0010
#define mmWRAP_START_DIR 0x0014
#define mmCIF_CNTL 0x0018
#define mmCFGREG_BASE 0x001C
#define mmCIF_IO 0x0020
#define mmCIF_READ_DBG 0x0024
#define mmCIF_WRITE_DBG 0x0028
#define cfgIND_ADDR_A_0 0x0000
#define cfgIND_ADDR_A_1 0x0001
#define cfgIND_ADDR_A_2 0x0002
#define cfgIND_DATA_A 0x0003
#define cfgREG_BASE 0x0004
#define cfgINTF_CNTL 0x0005
#define cfgSTATUS 0x0006
#define cfgCPU_DEFAULTS 0x0007
#define cfgIND_ADDR_B_0 0x0008
#define cfgIND_ADDR_B_1 0x0009
#define cfgIND_ADDR_B_2 0x000A
#define cfgIND_DATA_B 0x000B
#define cfgPM4_RPTR 0x000C
#define cfgSCRATCH 0x000D
#define cfgPM4_WRPTR_0 0x000E
#define cfgPM4_WRPTR_1 0x000F
/* Block CIF End: */
/* Block CP Start: */
#define mmSCRATCH_UMSK 0x0280
#define mmSCRATCH_ADDR 0x0284
#define mmGEN_INT_CNTL 0x0200
#define mmGEN_INT_STATUS 0x0204
/* Block CP End: */
/* Block DISPLAY Start: */
#define mmLCD_FORMAT 0x0410
#define mmGRAPHIC_CTRL 0x0414
#define mmGRAPHIC_OFFSET 0x0418
#define mmGRAPHIC_PITCH 0x041C
#define mmCRTC_TOTAL 0x0420
#define mmACTIVE_H_DISP 0x0424
#define mmACTIVE_V_DISP 0x0428
#define mmGRAPHIC_H_DISP 0x042C
#define mmGRAPHIC_V_DISP 0x0430
#define mmVIDEO_CTRL 0x0434
#define mmGRAPHIC_KEY 0x0438
#define mmBRIGHTNESS_CNTL 0x045C
#define mmDISP_INT_CNTL 0x0488
#define mmCRTC_SS 0x048C
#define mmCRTC_LS 0x0490
#define mmCRTC_REV 0x0494
#define mmCRTC_DCLK 0x049C
#define mmCRTC_GS 0x04A0
#define mmCRTC_VPOS_GS 0x04A4
#define mmCRTC_GCLK 0x04A8
#define mmCRTC_GOE 0x04AC
#define mmCRTC_FRAME 0x04B0
#define mmCRTC_FRAME_VPOS 0x04B4
#define mmGPIO_DATA 0x04B8
#define mmGPIO_CNTL1 0x04BC
#define mmGPIO_CNTL2 0x04C0
#define mmLCDD_CNTL1 0x04C4
#define mmLCDD_CNTL2 0x04C8
#define mmGENLCD_CNTL1 0x04CC
#define mmGENLCD_CNTL2 0x04D0
#define mmDISP_DEBUG 0x04D4
#define mmDISP_DB_BUF_CNTL 0x04D8
#define mmDISP_CRC_SIG 0x04DC
#define mmCRTC_DEFAULT_COUNT 0x04E0
#define mmLCD_BACKGROUND_COLOR 0x04E4
#define mmCRTC_PS2 0x04E8
#define mmCRTC_PS2_VPOS 0x04EC
#define mmCRTC_PS1_ACTIVE 0x04F0
#define mmCRTC_PS1_NACTIVE 0x04F4
#define mmCRTC_GCLK_EXT 0x04F8
#define mmCRTC_ALW 0x04FC
#define mmCRTC_ALW_VPOS 0x0500
#define mmCRTC_PSK 0x0504
#define mmCRTC_PSK_HPOS 0x0508
#define mmCRTC_CV4_START 0x050C
#define mmCRTC_CV4_END 0x0510
#define mmCRTC_CV4_HPOS 0x0514
#define mmCRTC_ECK 0x051C
#define mmREFRESH_CNTL 0x0520
#define mmGENLCD_CNTL3 0x0524
#define mmGPIO_DATA2 0x0528
#define mmGPIO_CNTL3 0x052C
#define mmGPIO_CNTL4 0x0530
#define mmCHIP_STRAP 0x0534
#define mmDISP_DEBUG2 0x0538
#define mmDEBUG_BUS_CNTL 0x053C
#define mmGAMMA_VALUE1 0x0540
#define mmGAMMA_VALUE2 0x0544
#define mmGAMMA_SLOPE 0x0548
#define mmGEN_STATUS 0x054C
#define mmHW_INT 0x0550
/* Block DISPLAY End: */
/* Block GFX Start: */
#define mmBRUSH_OFFSET 0x108C
#define mmBRUSH_Y_X 0x1074
#define mmDEFAULT_PITCH_OFFSET 0x10A0
#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
#define mmGLOBAL_ALPHA 0x1210
#define mmFILTER_COEF 0x1214
#define mmMVC_CNTL_START 0x11E0
#define mmE2_ARITHMETIC_CNTL 0x1220
#define mmENG_CNTL 0x13E8
#define mmENG_PERF_CNT 0x13F0
/* Block GFX End: */
/* Block IDCT Start: */
#define mmIDCT_RUNS 0x0C00
#define mmIDCT_LEVELS 0x0C04
#define mmIDCT_CONTROL 0x0C3C
#define mmIDCT_AUTH_CONTROL 0x0C08
#define mmIDCT_AUTH 0x0C0C
/* Block IDCT End: */
/* Block MC Start: */
#define mmMEM_CNTL 0x0180
#define mmMEM_ARB 0x0184
#define mmMC_FB_LOCATION 0x0188
#define mmMEM_EXT_CNTL 0x018C
#define mmMC_EXT_MEM_LOCATION 0x0190
#define mmMEM_EXT_TIMING_CNTL 0x0194
#define mmMEM_SDRAM_MODE_REG 0x0198
#define mmMEM_IO_CNTL 0x019C
#define mmMC_DEBUG 0x01A0
#define mmMC_BIST_CTRL 0x01A4
#define mmMC_BIST_COLLAR_READ 0x01A8
#define mmTC_MISMATCH 0x01AC
#define mmMC_PERF_MON_CNTL 0x01B0
#define mmMC_PERF_COUNTERS 0x01B4
/* Block MC End: */
/* Block BM Start: */
#define mmBM_EXT_MEM_BANDWIDTH 0x0A00
#define mmBM_OFFSET 0x0A04
#define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
#define mmBM_MEM_EXT_CNTL 0x0A0C
#define mmBM_MEM_MODE_REG 0x0A10
#define mmBM_MEM_IO_CNTL 0x0A18
#define mmBM_CONFIG 0x0A1C
#define mmBM_STATUS 0x0A20
#define mmBM_DEBUG 0x0A24
#define mmBM_PERF_MON_CNTL 0x0A28
#define mmBM_PERF_COUNTERS 0x0A2C
#define mmBM_PERF2_MON_CNTL 0x0A30
#define mmBM_PERF2_COUNTERS 0x0A34
/* Block BM End: */
/* Block RBBM Start: */
#define mmWAIT_UNTIL 0x1400
#define mmISYNC_CNTL 0x1404
#define mmRBBM_CNTL 0x0144
#define mmNQWAIT_UNTIL 0x0150
/* Block RBBM End: */
/* Block CG Start: */
#define mmCLK_PIN_CNTL 0x0080
#define mmPLL_REF_FB_DIV 0x0084
#define mmPLL_CNTL 0x0088
#define mmSCLK_CNTL 0x008C
#define mmPCLK_CNTL 0x0090
#define mmCLK_TEST_CNTL 0x0094
#define mmPWRMGT_CNTL 0x0098
#define mmPWRMGT_STATUS 0x009C
/* Block CG End: */
/* default value definitions */
#define defWRAP_TOP_DIR 0x00000000
#define defWRAP_START_DIR 0x00000000
#define defCFGREG_BASE 0x00000000
#define defCIF_IO 0x000C0902
#define defINTF_CNTL 0x00000011
#define defCPU_DEFAULTS 0x00000006
#define defHW_INT 0x00000000
#define defMC_EXT_MEM_LOCATION 0x07ff0000
#define defTC_MISMATCH 0x00000000
#define W100_CFG_BASE 0x0
#define W100_CFG_LEN 0x10
#define W100_REG_BASE 0x10000
#define W100_REG_LEN 0x2000
#define MEM_INT_BASE_VALUE 0x100000
#define MEM_EXT_BASE_VALUE 0x800000
#define MEM_INT_SIZE 0x05ffff
#define MEM_WINDOW_BASE 0x100000
#define MEM_WINDOW_SIZE 0xf00000
#define WRAP_BUF_BASE_VALUE 0x80000
#define WRAP_BUF_TOP_VALUE 0xbffff
#define CHIP_ID_W100 0x57411002
#define CHIP_ID_W3200 0x56441002
#define CHIP_ID_W3220 0x57441002
/* Register structure definitions */
struct wrap_top_dir_t {
unsigned long top_addr : 23;
unsigned long : 9;
} __attribute__((packed));
union wrap_top_dir_u {
unsigned long val : 32;
struct wrap_top_dir_t f;
} __attribute__((packed));
struct wrap_start_dir_t {
unsigned long start_addr : 23;
unsigned long : 9;
} __attribute__((packed));
union wrap_start_dir_u {
unsigned long val : 32;
struct wrap_start_dir_t f;
} __attribute__((packed));
struct cif_cntl_t {
unsigned long swap_reg : 2;
unsigned long swap_fbuf_1 : 2;
unsigned long swap_fbuf_2 : 2;
unsigned long swap_fbuf_3 : 2;
unsigned long pmi_int_disable : 1;
unsigned long pmi_schmen_disable : 1;
unsigned long intb_oe : 1;
unsigned long en_wait_to_compensate_dq_prop_dly : 1;
unsigned long compensate_wait_rd_size : 2;
unsigned long wait_asserted_timeout_val : 2;
unsigned long wait_masked_val : 2;
unsigned long en_wait_timeout : 1;
unsigned long en_one_clk_setup_before_wait : 1;
unsigned long interrupt_active_high : 1;
unsigned long en_overwrite_straps : 1;
unsigned long strap_wait_active_hi : 1;
unsigned long lat_busy_count : 2;
unsigned long lat_rd_pm4_sclk_busy : 1;
unsigned long dis_system_bits : 1;
unsigned long dis_mr : 1;
unsigned long cif_spare_1 : 4;
} __attribute__((packed));
union cif_cntl_u {
unsigned long val : 32;
struct cif_cntl_t f;
} __attribute__((packed));
struct cfgreg_base_t {
unsigned long cfgreg_base : 24;
unsigned long : 8;
} __attribute__((packed));
union cfgreg_base_u {
unsigned long val : 32;
struct cfgreg_base_t f;
} __attribute__((packed));
struct cif_io_t {
unsigned long dq_srp : 1;
unsigned long dq_srn : 1;
unsigned long dq_sp : 4;
unsigned long dq_sn : 4;
unsigned long waitb_srp : 1;
unsigned long waitb_srn : 1;
unsigned long waitb_sp : 4;
unsigned long waitb_sn : 4;
unsigned long intb_srp : 1;
unsigned long intb_srn : 1;
unsigned long intb_sp : 4;
unsigned long intb_sn : 4;
unsigned long : 2;
} __attribute__((packed));
union cif_io_u {
unsigned long val : 32;
struct cif_io_t f;
} __attribute__((packed));
struct cif_read_dbg_t {
unsigned long unpacker_pre_fetch_trig_gen : 2;
unsigned long dly_second_rd_fetch_trig : 1;
unsigned long rst_rd_burst_id : 1;
unsigned long dis_rd_burst_id : 1;
unsigned long en_block_rd_when_packer_is_not_emp
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