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|
/*
* Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
*
* Copyright 2006-2010 Analog Devices Inc.
* Licensed under the GPL-2.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/device.h>
#include <linux/backlight.h>
#include <linux/lcd.h>
#include <linux/i2c.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <asm/blackfin.h>
#include <asm/irq.h>
#include <asm/dpmc.h>
#include <asm/dma.h>
#include <asm/portmux.h>
#define NO_BL 1
#define MAX_BRIGHENESS 95
#define MIN_BRIGHENESS 5
#define NBR_PALETTE 256
static const unsigned short ppi_pins[] = {
P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
};
static unsigned char *fb_buffer; /* RGB Buffer */
static unsigned long *dma_desc_table;
static int t_conf_done, lq035_open_cnt;
static DEFINE_SPINLOCK(bfin_lq035_lock);
static int landscape;
module_param(landscape, int, 0);
MODULE_PARM_DESC(landscape,
"LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
static int bgr;
module_param(bgr, int, 0);
MODULE_PARM_DESC(bgr,
"BGR use 16-bit BGR-565 instead of RGB-565");
static int nocursor = 1;
module_param(nocursor, int, 0644);
MODULE_PARM_DESC(nocursor, "cursor enable/disable");
static unsigned long current_brightness; /* backlight */
/* AD5280 vcomm */
static unsigned char vcomm_value = 150;
static struct i2c_client *ad5280_client;
static void set_vcomm(void)
{
int nr;
if (!ad5280_client)
return;
nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
if (nr)
pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
}
static int ad5280_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
int ret;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
return -EIO;
}
ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
if (ret) {
dev_err(&client->dev, "write fail: %d\n", ret);
return ret;
}
ad5280_client = client;
return 0;
}
static int ad5280_remove(struct i2c_client *client)
{
ad5280_client = NULL;
return 0;
}
static const struct i2c_device_id ad5280_id[] = {
{"bf537-lq035-ad5280", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, ad5280_id);
static struct i2c_driver ad5280_driver = {
.driver = {
.name = "bf537-lq035-ad5280",
},
.probe = ad5280_probe,
.remove = ad5280_remove,
.id_table = ad5280_id,
};
#ifdef CONFIG_PNAV10
#define MOD GPIO_PH13
#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
#define TIMDIS_LP TIMDIS0
#define TIMEN_LP TIMEN0
#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
#define TIMDIS_SPS TIMDIS1
#define TIMEN_SPS TIMEN1
#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
#define TIMDIS_SP TIMDIS5
#define TIMEN_SP TIMEN5
#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
#define TIMDIS_PS_CLS TIMDIS2
#define TIMEN_PS_CLS TIMEN2
#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
#define TIMDIS_REV TIMDIS3
#define TIMEN_REV TIMEN3
#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
#else
#define UD GPIO_PF13 /* Up / Down */
#define MOD GPIO_PF10
#define LBR GPIO_PF14 /* Left Right */
#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
#define TIMDIS_LP TIMDIS6
#define TIMEN_LP TIMEN6
#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
#define TIMDIS_SPS TIMDIS1
#define TIMEN_SPS TIMEN1
#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
#define TIMDIS_SP TIMDIS0
#define TIMEN_SP TIMEN0
#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
#define TIMDIS_PS_CLS TIMDIS7
#define TIMEN_PS_CLS TIMEN7
#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
#define TIMDIS_REV TIMDIS5
#define TIMEN_REV TIMEN5
#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
#endif
#define LCD_X_RES 240 /* Horizontal Resolution */
#define LCD_Y_RES 320 /* Vertical Resolution */
#define LCD_BBP 16 /* Bit Per Pixel */
/* the LCD and the DMA start counting differently;
* since one starts at 0 and the other starts at 1,
* we have a difference of 1 between START_LINES
* and U_LINES.
*/
#define START_LINES 8 /* lines for field flyback or field blanking signal */
#define U_LINES 9 /* number of undisplayed blanking lines */
#define FRAMES_PER_SEC (60)
#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
#define PPI_DELAY_VALUE (0)
#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
static void start_timers(void) /* CHECK with HW */
{
unsigned long flags;
local_irq_save(flags);
bfin_write_TIMER_ENABLE(TIMEN_REV);
SSYNC();
while (bfin_read_TIMER_REV_COUNTER() <= 11)
continue;
bfin_write_TIMER_ENABLE(TIMEN_LP);
SSYNC();
while (bfin_read_TIMER_LP_COUNTER() < 3)
continue;
bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
SSYNC();
t_conf_done = 1;
local_irq_restore(flags);
}
static void config_timers(void)
{
/* Stop timers */
bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
|