path: root/drivers/video/aty/radeon_accel.c

#include "radeonfb.h"

/* the accelerated functions here are patterned after the 
 * "ACCEL_MMIO" ifdef branches in XFree86
 * --dte
 */

#define FLUSH_CACHE_WORKAROUND	1

void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
{
	int i;

	for (i=0; i<2000000; i++) {
		rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f;
		if (rinfo->fifo_free >= entries)
			return;
		udelay(10);
	}
	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
	/* XXX Todo: attempt to reset the engine */
}

static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
	if (entries <= rinfo->fifo_free)
		rinfo->fifo_free -= entries;
	else
		radeon_fifo_update_and_wait(rinfo, entries);
}

static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg,
				     u32 *cache, u32 new_val)
{
	if (new_val == *cache)
		return;
	*cache = new_val;
	radeon_fifo_wait(rinfo, 1);
	OUTREG(reg, new_val);
}

static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 
				   const struct fb_fillrect *region)
{
	radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
			  rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P);
	radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
			  DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
	radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache,
			  region->color);

	/* Ensure the dst cache is flushed and the engine idle before
	 * issuing the operation.
	 *
	 * This works around engine lockups on some cards
	 */
#if FLUSH_CACHE_WORKAROUND
	radeon_fifo_wait(rinfo, 2);
	OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
	OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
#endif
	radeon_fifo_wait(rinfo, 2);
	OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
	OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
}

void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
{
	struct radeonfb_info *rinfo = info->par;
	struct fb_fillrect modded;
	int vxres, vyres;
  
	WARN_ON(rinfo->gfx_mode);
	if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
		return;
	if (info->flags & FBINFO_HWACCEL_DISABLED) {
		cfb_fillrect(info, region);
		return;
	}

	vxres = info->var.xres_virtual;
	vyres = info->var.yres_virtual;

	memcpy(&modded, region, sizeof(struct fb_fillrect));

	if(!modded.width || !modded.height ||
	   modded.dx >= vxres || modded.dy >= vyres)
		return;
  
	if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
	if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;

	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
	    info->fix.visual == FB_VISUAL_DIRECTCOLOR )
		modded.color = ((u32 *) (info->pseudo_palette))[region->color];

	radeonfb_prim_fillrect(rinfo, &modded);
}

static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo, 
				   const struct fb_copyarea *area)
{
	int xdir, ydir;
	u32 sx, sy, dx, dy, w, h;

	w = area->width; h = area->height;
	dx = area->dx; dy = area->dy;
	sx = area->sx; sy = area->sy;
	xdir = sx - dx;
	ydir = sy - dy;

	if ( xdir < 0 ) { sx += w-1; dx += w-1; }
	if ( ydir < 0 ) { sy += h-1; dy += h-1; }

	radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
			  rinfo->dp_gui_mc_base |
			  GMC_BRUSH_NONE |
			  GMC_SRC_DATATYPE_COLOR |
			  ROP3_S |
			  DP_SRC_SOURCE_MEMORY);
	radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
			  (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) |
			  (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));

#if FLUSH_CACHE_WORKAROUND
	radeon_fifo_wait(rinfo, 2);
	OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
	OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
#endif
	radeon_fifo_wait(rinfo, 3);
	OUTREG(SRC_Y_X, (sy << 16) | sx);
	OUTREG(DST_Y_X, (dy << 16) | dx);
	OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
}


void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
	struct radeonfb_info *rinfo = info->par;
	struct fb_copyarea modded;
	u32 vxres, vyres;
	modded.sx = area->sx;
	modded.sy = area->sy;
	modded.dx = area->dx;
	modded.dy = area->dy;
	modded.width  = area->width;
	modded.height = area->height;
  
	WARN_ON(rinfo->gfx_mode);
	if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
		return;
	if (info->flags & FBINFO_HWACCEL_DISABLED) {
		cfb_copyarea(info, area);
		return;
	}

	vxres = info->var.xres_virtual;
	vyres = info->var.yres_virtual;

	if(!modded.width || !modded.height ||
	   modded.sx >= vxres || modded.sy >= vyres ||
	   modded.dx >= vxres || modded.dy >= vyres)
		return;
  
	if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
	if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
	if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
	if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
  
	radeonfb_prim_copyarea(rinfo, &modded);
}

static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
				    const struct fb_image *image,
				    u32 fg, u32 bg)
{
	unsigned int dwords;
	u32 *bits;

	radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
			  rinfo->dp_gui_mc_base |
			  GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE |
			  GMC_SRC_DATATYPE_MONO_FG_BG |
			  ROP3_S |
			  GMC_BYTE_ORDER_MSB_TO_LSB |
			  DP_SRC_SOURCE_HOST_DATA);