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|
// SPDX-License-Identifier: GPL-2.0
/**
* typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
*
* Copyright (C) 2017 Intel Corporation
* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/usb/tcpm.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mfd/intel_soc_pmic.h>
/* Register offsets */
#define WCOVE_CHGRIRQ0 0x4e09
#define USBC_CONTROL1 0x7001
#define USBC_CONTROL2 0x7002
#define USBC_CONTROL3 0x7003
#define USBC_CC1_CTRL 0x7004
#define USBC_CC2_CTRL 0x7005
#define USBC_STATUS1 0x7007
#define USBC_STATUS2 0x7008
#define USBC_STATUS3 0x7009
#define USBC_CC1 0x700a
#define USBC_CC2 0x700b
#define USBC_CC1_STATUS 0x700c
#define USBC_CC2_STATUS 0x700d
#define USBC_IRQ1 0x7015
#define USBC_IRQ2 0x7016
#define USBC_IRQMASK1 0x7017
#define USBC_IRQMASK2 0x7018
#define USBC_PDCFG2 0x701a
#define USBC_PDCFG3 0x701b
#define USBC_PDSTATUS 0x701c
#define USBC_RXSTATUS 0x701d
#define USBC_RXINFO 0x701e
#define USBC_TXCMD 0x701f
#define USBC_TXINFO 0x7020
#define USBC_RX_DATA 0x7028
#define USBC_TX_DATA 0x7047
/* Register bits */
#define USBC_CONTROL1_MODE_MASK 0x3
#define USBC_CONTROL1_MODE_SNK 0
#define USBC_CONTROL1_MODE_SNKACC 1
#define USBC_CONTROL1_MODE_SRC 2
#define USBC_CONTROL1_MODE_SRCACC 3
#define USBC_CONTROL1_MODE_DRP 4
#define USBC_CONTROL1_MODE_DRPACC 5
#define USBC_CONTROL1_MODE_TEST 7
#define USBC_CONTROL1_CURSRC_MASK 0xc
#define USBC_CONTROL1_CURSRC_UA_0 (0 << 3)
#define USBC_CONTROL1_CURSRC_UA_80 (1 << 3)
#define USBC_CONTROL1_CURSRC_UA_180 (2 << 3)
#define USBC_CONTROL1_CURSRC_UA_330 (3 << 3)
#define USBC_CONTROL1_DRPTOGGLE_RANDOM 0xe0
#define USBC_CONTROL2_UNATT_SNK BIT(0)
#define USBC_CONTROL2_UNATT_SRC BIT(1)
#define USBC_CONTROL2_DIS_ST BIT(2)
#define USBC_CONTROL3_DET_DIS BIT(0)
#define USBC_CONTROL3_PD_DIS BIT(1)
#define USBC_CONTROL3_RESETPHY BIT(2)
#define USBC_CC_CTRL_PU_EN BIT(0)
#define USBC_CC_CTRL_VCONN_EN BIT(1)
#define USBC_CC_CTRL_TX_EN BIT(2)
#define USBC_CC_CTRL_PD_EN BIT(3)
#define USBC_CC_CTRL_CDET_EN BIT(4)
#define USBC_CC_CTRL_RDET_EN BIT(5)
#define USBC_CC_CTRL_ADC_EN BIT(6)
#define USBC_CC_CTRL_VBUSOK BIT(7)
#define USBC_STATUS1_DET_ONGOING BIT(6)
#define USBC_STATUS1_RSLT(r) ((r) & 0xf)
#define USBC_RSLT_NOTHING 0
#define USBC_RSLT_SRC_DEFAULT 1
#define USBC_RSLT_SRC_1_5A 2
#define USBC_RSLT_SRC_3_0A 3
#define USBC_RSLT_SNK 4
#define USBC_RSLT_DEBUG_ACC 5
#define USBC_RSLT_AUDIO_ACC 6
#define USBC_RSLT_UNDEF 15
#define USBC_STATUS1_ORIENT(r) (((r) >> 4) & 0x3)
#define USBC_ORIENT_NORMAL 1
#define USBC_ORIENT_REVERSE 2
#define USBC_STATUS2_VBUS_REQ BIT(5)
#define UCSC_CC_STATUS_SNK_RP BIT(0)
#define UCSC_CC_STATUS_PWRDEFSNK BIT(1)
#define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2)
#define UCSC_CC_STATUS_PWR_3A_SNK BIT(3)
#define UCSC_CC_STATUS_SRC_RP BIT(4)
#define UCSC_CC_STATUS_RX(r) (((r) >> 5) & 0x3)
#define USBC_CC_STATUS_RD 1
#define USBC_CC_STATUS_RA 2
#define USBC_IRQ1_ADCDONE1 BIT(2)
#define USBC_IRQ1_OVERTEMP BIT(1)
#define USBC_IRQ1_SHORT BIT(0)
#define USBC_IRQ2_CC_CHANGE BIT(7)
#define USBC_IRQ2_RX_PD BIT(6)
#define USBC_IRQ2_RX_HR BIT(5)
#define USBC_IRQ2_RX_CR BIT(4)
#define USBC_IRQ2_TX_SUCCESS BIT(3)
#define USBC_IRQ2_TX_FAIL BIT(2)
#define USBC_IRQMASK1_ALL (USBC_IRQ1_ADCDONE1 | USBC_IRQ1_OVERTEMP | \
USBC_IRQ1_SHORT)
#define USBC_IRQMASK2_ALL (USBC_IRQ2_CC_CHANGE | USBC_IRQ2_RX_PD | \
USBC_IRQ2_RX_HR | USBC_IRQ2_RX_CR | \
USBC_IRQ2_TX_SUCCESS | USBC_IRQ2_TX_FAIL)
#define USBC_PDCFG2_SOP BIT(0)
#define USBC_PDCFG2_SOP_P BIT(1)
#define USBC_PDCFG2_SOP_PP BIT(2)
#define USBC_PDCFG2_SOP_P_DEBUG BIT(3)
#define USBC_PDCFG2_SOP_PP_DEBUG BIT(4)
#define USBC_PDCFG3_DATAROLE_SHIFT 1
#define USBC_PDCFG3_SOP_SHIFT 2
#define USBC_RXSTATUS_RXCLEAR BIT(0)
#define USBC_RXSTATUS_RXDATA BIT(7)
#define USBC_RXINFO_RXBYTES(i) (((i) >> 3) & 0x1f)
#define USBC_TXCMD_BUF_RDY BIT(0)
#define USBC_TXCMD_START BIT(1)
#define USBC_TXCMD_NOP (0 << 5)
#define USBC_TXCMD_MSG (1 << 5)
#define USBC_TXCMD_CR (2 << 5)
#define USBC_TXCMD_HR (3 << 5)
#define USBC_TXCMD_BIST (4 << 5)
#define USBC_TXINFO_RETRIES(d) (d << 3)
struct wcove_typec {
struct mutex lock; /* device lock */
struct device *dev;
struct regmap *regmap;
guid_t guid;
bool vbus;
struct tcpc_dev tcpc;
struct tcpm_port *tcpm;
};
#define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)
enum wcove_typec_func {
WCOVE_FUNC_DRIVE_VBUS = 1,
WCOVE_FUNC_ORIENTATION,
WCOVE_FUNC_ROLE,
WCOVE_FUNC_DRIVE_VCONN,
};
enum wcove_typec_orientation {
WCOVE_ORIENTATION_NORMAL,
WCOVE_ORIENTATION_REVERSE,
};
enum wcove_typec_role {
WCOVE_ROLE_HOST,
WCOVE_ROLE_DEVICE,
};
#define WCOVE_DSM_UUID "482383f0-2876-4e49-8685-db66211af037"
static int wcove_typec_func(struct wcove_typec *wcove,
enum wcove_typec_func func, int param)
{
union acpi_object *obj;
union acpi_object tmp;
union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
tmp.type = ACPI_TYPE_INTEGER;
tmp.integer.value = param;
obj = acpi_evaluate_dsm(ACPI_HANDLE(wcove->dev), &wcove->guid, 1, func,
&argv4);
if (!obj) {
dev_err(wcove->dev, "%s: failed to evaluate _DSM\n", __func__);
return -EIO;
}
ACPI_FREE(obj);
return 0;
}
static int wcove_init(struct tcpc_dev *tcpc)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
int ret;
/* Unmask everything */
ret = regmap_write(wcove->regmap, USBC_IRQMASK1, 0);
if (ret)
return ret;
return regmap_write(wcove->regmap, USBC_IRQMASK2, 0);
}
static int wcove_get_vbus(struct tcpc_dev *tcpc)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
unsigned int cc1ctrl;
int ret;
ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
if (ret)
return ret;
wcove->vbus = !!(cc1ctrl & USBC_CC_CTRL_VBUSOK);
return wcove->vbus;
}
static int wcove_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VBUS, on);
}
static int wcove_set_vconn(struct tcpc_dev *tcpc, bool on)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, on);
}
static enum typec_cc_status wcove_to_typec_cc(unsigned int cc)
{
if (cc & UCSC_CC_STATUS_SNK_RP) {
if (cc & UCSC_CC_STATUS_PWRDEFSNK)
return TYPEC_CC_RP_DEF;
else if (cc & UCSC_CC_STATUS_PWR_1P5A_SNK)
return TYPEC_CC_RP_1_5;
else if (cc & UCSC_CC_STATUS_PWR_3A_SNK)
return TYPEC_CC_RP_3_0;
} else {
switch (UCSC_CC_STATUS_RX(cc)) {
case USBC_CC_STATUS_RD:
return TYPEC_CC_RD;
case USBC_CC_STATUS_RA:
return TYPEC_CC_RA;
default:
break;
}
}
return TYPEC_CC_OPEN;
}
static int wcove_get_cc(struct tcpc_dev *tcpc, enum typec_cc_status *cc1,
enum typec_cc_status *cc2)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
unsigned int cc1_status;
unsigned int cc2_status;
int ret;
ret = regmap_read(wcove->regmap, USBC_CC1_STATUS, &cc1_status);
if (ret)
return ret;
ret = regmap_read(wcove->regmap, USBC_CC2_STATUS, &cc2_status);
if (ret)
return ret;
*cc1 = wcove_to_typec_cc(cc1_status);
*cc2 = wcove_to_typec_cc(cc2_status);
return 0;
}
static int wcove_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
{
/* XXX: Relying on the HW FSM to configure things correctly for now */
return 0;
}
static int wcove_set_polarity(struct tcpc_dev *tcpc, enum typec_cc_polarity pol)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
return wcove_typec_func(wcove, WCOVE_FUNC_ORIENTATION, pol);
}
static int wcove_set_current_limit(struct tcpc_dev *tcpc, u32 max_ma, u32 mv)
{
return 0;
}
static int wcove_set_roles(struct tcpc_dev *tcpc, bool attached,
enum typec_role role, enum typec_data_role data)
{
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
unsigned int val;
int ret;
ret = wcove_typec_func(wcove, WCOVE_FUNC_ROLE, data ==
|