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#ifndef __LINUX_FOTG210_H
#define __LINUX_FOTG210_H
#include <linux/usb/ehci-dbgp.h>
/* definitions used for the EHCI driver */
/*
* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
* __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
* the host controller implementation.
*
* To facilitate the strongest possible byte-order checking from "sparse"
* and so on, we use __leXX unless that's not practical.
*/
#define __hc32 __le32
#define __hc16 __le16
/* statistics can be kept for tuning/monitoring */
struct fotg210_stats {
/* irq usage */
unsigned long normal;
unsigned long error;
unsigned long iaa;
unsigned long lost_iaa;
/* termination of urbs from core */
unsigned long complete;
unsigned long unlink;
};
/* fotg210_hcd->lock guards shared data against other CPUs:
* fotg210_hcd: async, unlink, periodic (and shadow), ...
* usb_host_endpoint: hcpriv
* fotg210_qh: qh_next, qtd_list
* fotg210_qtd: qtd_list
*
* Also, hold this lock when talking to HC registers or
* when updating hw_* fields in shared qh/qtd/... structures.
*/
#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
/*
* fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
* controller may be doing DMA. Lower values mean there's no DMA.
*/
enum fotg210_rh_state {
FOTG210_RH_HALTED,
FOTG210_RH_SUSPENDED,
FOTG210_RH_RUNNING,
FOTG210_RH_STOPPING
};
/*
* Timer events, ordered by increasing delay length.
* Always update event_delays_ns[] and event_handlers[] (defined in
* ehci-timer.c) in parallel with this list.
*/
enum fotg210_hrtimer_event {
FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
};
#define FOTG210_HRTIMER_NO_EVENT 99
struct fotg210_hcd { /* one per controller */
/* timing support */
enum fotg210_hrtimer_event next_hrtimer_event;
unsigned enabled_hrtimer_events;
ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
struct hrtimer hrtimer;
int PSS_poll_count;
int ASS_poll_count;
int died_poll_count;
/* glue to PCI and HCD framework */
struct fotg210_caps __iomem *caps;
struct fotg210_regs __iomem *regs;
struct ehci_dbg_port __iomem *debug;
__u32 hcs_params; /* cached register copy */
spinlock_t lock;
enum fotg210_rh_state rh_state;
/* general schedule support */
bool scanning:1;
bool need_rescan:1;
bool intr_unlinking:1;
bool async_unlinking:1;
bool shutdown:1;
struct fotg210_qh *qh_scan_next;
/* async schedule support */
struct fotg210_qh *async;
struct fotg210_qh *dummy; /* For AMD quirk use */
struct fotg210_qh *async_unlink;
struct fotg210_qh *async_unlink_last;
struct fotg210_qh *async_iaa;
unsigned async_unlink_cycle;
unsigned async_count; /* async activity count */
/* periodic schedule support */
#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
unsigned periodic_size;
__hc32 *periodic; /* hw periodic table */
dma_addr_t periodic_dma;
struct list_head intr_qh_list;
unsigned i_thresh; /* uframes HC might cache */
union fotg210_shadow *pshadow; /* mirror hw periodic table */
struct fotg210_qh *intr_unlink;
struct fotg210_qh *intr_unlink_last;
unsigned intr_unlink_cycle;
unsigned now_frame; /* frame from HC hardware */
unsigned next_frame; /* scan periodic, start here */
unsigned intr_count; /* intr activity count */
unsigned isoc_count; /* isoc activity count */
unsigned periodic_count; /* periodic activity count */
/* max periodic time per uframe */
unsigned uframe_periodic_max;
/* list of itds completed while now_frame was still active */
struct list_head cached_itd_list;
struct fotg210_itd *last_itd_to_free;
/* per root hub port */
unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
/* bit vectors (one bit per port)
* which ports were already suspended at the start of a bus suspend
*/
unsigned long bus_suspended;
/* which ports are edicated to the companion controller */
unsigned long companion_ports;
/* which ports are owned by the companion during a bus suspend */
unsigned long owned_ports;
/* which ports have the change-suspend feature turned on */
unsigned long port_c_suspend;
/* which ports are suspended */
unsigned long suspended_ports;
/* which ports have started to resume */
unsigned long resuming_ports;
/* per-HC memory pools (could be per-bus, but ...) */
struct dma_pool *qh_pool; /* qh per active urb */
struct dma_pool *qtd_pool; /* one or more per qh */
struct dma_pool *itd_pool; /* itd per iso urb */
unsigned random_frame;
unsigned long next_statechange;
ktime_t last_periodic_enable;
u32 command;
/* SILICON QUIRKS */
unsigned need_io_watchdog:1;
unsigned fs_i_thresh:1; /* Intel iso scheduling */
u8 sbrn; /* packed release number */
/* irq statistics */
#ifdef FOTG210_STATS
struct fotg210_stats stats;
# define COUNT(x) ((x)++)
#else
# define COUNT(x)
#endif
/* debug files */
struct dentry *debug_dir;
};
/* convert between an HCD pointer and the corresponding FOTG210_HCD */
static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
{
return (struct fotg210_hcd *)(hcd->hcd_priv);
}
static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
{
return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
}
/*-------------------------------------------------------------------------*/
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
/* Section 2.2 Host Controller Capability Registers */
struct fotg210_caps {
/* these fields are specified as 8 and 16 bit registers,
* but some hosts can't perform 8 or 16 bit PCI accesses.
* some hosts treat caplength and hciversion as parts of a 32-bit
* register, others treat them as two separate registers, this
* affects the memory map for big endian controllers.
*/
u32 hc_capbase;
#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
(fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
(fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
u32 hcs_params; /* HCSPARAMS - offset 0x4 */
#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
u32 hcc_params; /* HCCPARAMS - offset 0x8 */
#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
u8 portroute[8]; /* nibbles for routing - offset 0xC */
};
/* Section 2.3 Host Controller Operational Registers */
struct fotg210_regs {
/* USBCMD: offset 0x00 */
u32 command;
/* EHCI 1.1 addendum */
/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
#define CMD_PARK (1<<11) /* enable "park" on async qh */
#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
#define CMD_ASE (1<<5) /* async schedule enable */
#define CMD_PSE (1<<4) /* periodic schedule enable */
/* 3:2 is periodic frame list size */
#define CMD_RESET (1<<1) /* reset HC not bus */
#define CMD_RUN (1<<0) /* start/stop HC */
/* USBSTS: offset 0x04 */
u32 status;
#define STS_ASS (1<<15) /* Async Schedule Status */
#define STS_PSS (1<<14) /* Periodic Schedule Status */
#define STS_RECL (1<<13) /* Reclamation */
#define STS_HALT (1<<12) /* Not running (any reason) */
/* some bits reserved */
/* these STS_* flags are also intr_enable bits (USBINTR) */
#define STS_IAA (1<<5) /* Interrupted on async advance */
#define STS_FATAL (1<<4) /* such as some PCI access errors */
#define STS_FLR (1<<3) /* frame list rolled over */
#define STS_PCD (1<<2) /* port change detect */
#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
#define STS_INT (1<<0) /* "normal" completion (short, ...) */
/* USBINTR: offset 0x08 */
u32 intr_enable;
/* FRINDEX: offset 0x0C */
u32 frame_index; /* current microframe number */
/* CTRLDSSEGMENT: offset 0x10 */
u32 segment; /* address bits 63:32 if needed */
/* PERIODICLISTBASE: offset 0x14 */
u32 frame_list; /* points to periodic list */
/* ASYNCLISTADDR: offset 0x18 */
u32 async_next; /* address of next async queue head */
u32 reserved1;
/* PORTSC: offset 0x20 */
u32 port_status;
/* 31:23 reserved */
#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
#define PORT_RESET (1<<8) /* reset port */
#define PORT_SUSPEND (1<<7) /* suspend port */
#define PORT_RESUME (1<<6) /* resume it */
#define PORT_PEC (1<<3) /* port enable change */
#define PORT_PE (1<<2) /* port enable */
#define PORT_CSC (1<<1) /* connect status change */
#define PORT_CONNECT (1<<0) /* device connected */
#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
u32 reserved2[19];
/* OTGCSR: offet 0x70 */
u32 otgcsr;
#define OTGCSR_HOST_SPD_TYP (3 << 22)
#define OTGCSR_A_BUS_DROP (1 << 5)
#define OTGCSR_A_BUS_REQ (1 << 4)
/* OTGISR: offset 0x74 */
u32 otgisr;
#define OTGISR_OVC (1 << 10)
u32 reserved3[15];
/* GMIR: offset 0xB4 */
u32 gmir;
#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
#define GMIR_MHC_INT (1 << 2)
#define GMIR_MOTG_INT (1 << 1)
#define GMIR_MDEV_INT (1 << 0)
};
/*-------------------------------------------------------------------------*/
#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
/*
* EHCI Specification 0.95 Section 3.5
* QTD: describe data transfer components (buffer, direction, ...)
* See
|