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/*
* Driver for Comtrol RocketPort EXPRESS/INFINITY cards
*
* Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
*
* Inspired by, and loosely based on:
*
* ar933x_uart.c
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* rocketport_infinity_express-linux-1.20.tar.gz
* Copyright (C) 2004-2011 Comtrol, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/completion.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/sysrq.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/types.h>
#define DRV_NAME "rp2"
#define RP2_FW_NAME "rp2.fw"
#define RP2_UCODE_BYTES 0x3f
#define PORTS_PER_ASIC 16
#define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
#define UART_CLOCK 44236800
#define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
#define FIFO_SIZE 512
/* BAR0 registers */
#define RP2_FPGA_CTL0 0x110
#define RP2_FPGA_CTL1 0x11c
#define RP2_IRQ_MASK 0x1ec
#define RP2_IRQ_MASK_EN_m BIT(0)
#define RP2_IRQ_STATUS 0x1f0
/* BAR1 registers */
#define RP2_ASIC_SPACING 0x1000
#define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
#define RP2_PORT_BASE 0x000
#define RP2_PORT_SPACING 0x040
#define RP2_UCODE_BASE 0x400
#define RP2_UCODE_SPACING 0x80
#define RP2_CLK_PRESCALER 0xc00
#define RP2_CH_IRQ_STAT 0xc04
#define RP2_CH_IRQ_MASK 0xc08
#define RP2_ASIC_IRQ 0xd00
#define RP2_ASIC_IRQ_EN_m BIT(20)
#define RP2_GLOBAL_CMD 0xd0c
#define RP2_ASIC_CFG 0xd04
/* port registers */
#define RP2_DATA_DWORD 0x000
#define RP2_DATA_BYTE 0x008
#define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
#define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
#define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
#define RP2_DATA_BYTE_BREAK_m BIT(11)
/* This lets uart_insert_char() drop bytes received on a !CREAD port */
#define RP2_DUMMY_READ BIT(16)
#define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
RP2_DATA_BYTE_ERR_OVERRUN_m | \
RP2_DATA_BYTE_ERR_FRAMING_m | \
RP2_DATA_BYTE_BREAK_m)
#define RP2_RX_FIFO_COUNT 0x00c
#define RP2_TX_FIFO_COUNT 0x00e
#define RP2_CHAN_STAT 0x010
#define RP2_CHAN_STAT_RXDATA_m BIT(0)
#define RP2_CHAN_STAT_DCD_m BIT(3)
#define RP2_CHAN_STAT_DSR_m BIT(4)
#define RP2_CHAN_STAT_CTS_m BIT(5)
#define RP2_CHAN_STAT_RI_m BIT(6)
#define RP2_CHAN_STAT_OVERRUN_m BIT(13)
#define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
#define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
#define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
#define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
#define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
#define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
RP2_CHAN_STAT_CTS_CHANGED_m | \
RP2_CHAN_STAT_CD_CHANGED_m | \
RP2_CHAN_STAT_RI_CHANGED_m)
#define RP2_TXRX_CTL 0x014
#define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
#define RP2_TXRX_CTL_RXIRQ_m BIT(2)
#define RP2_TXRX_CTL_RX_TRIG_s 3
#define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_EN_m BIT(5)
#define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
#define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
#define RP2_TXRX_CTL_TX_TRIG_s 16
#define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
#define RP2_TXRX_CTL_TXIRQ_m BIT(19)
#define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
#define RP2_TXRX_CTL_TX_EN_m BIT(24)
#define RP2_TXRX_CTL_RTS_m BIT(25)
#define RP2_TXRX_CTL_DTR_m BIT(26)
#define RP2_TXRX_CTL_LOOP_m BIT(27)
#define RP2_TXRX_CTL_BREAK_m BIT(28)
#define RP2_TXRX_CTL_CMSPAR_m BIT(29)
#define RP2_TXRX_CTL_nPARODD_m BIT(30)
#define RP2_TXRX_CTL_PARENB_m BIT(31)
#define RP2_UART_CTL 0x018
#define RP2_UART_CTL_MODE_s 0
#define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
#define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
#define RP2_UART_CTL_FLUSH_RX_m BIT(3)
#define RP2_UART_CTL_FLUSH_TX_m BIT(4)
#define RP2_UART_CTL_RESET_CH_m BIT(5)
#define RP2_UART_CTL_XMIT_EN_m BIT(6)
#define RP2_UART_CTL_DATABITS_s 8
#define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_STOPBITS_m BIT(10)
#define RP2_BAUD 0x01c
/* ucode registers */
#define RP2_TX_SWFLOW 0x02
#define RP2_TX_SWFLOW_ena 0x81
#define RP2_TX_SWFLOW_dis 0x9d
#define RP2_RX_SWFLOW 0x0c
#define RP2_RX_SWFLOW_ena 0x81
#define RP2_RX_SWFLOW_dis 0x8d
#define RP2_RX_FIFO 0x37
#define RP2_RX_FIFO_ena 0x08
#define RP2_RX_FIFO_dis 0x81
static struct uart_driver rp2_uart_driver = {
.owner = THIS_MODULE,
.driver_name = DRV_NAME,
.dev_name = "ttyRP",
.nr = CONFIG_SERIAL_RP2_NR_UARTS,
};
struct rp2_card;
struct rp2_uart_port {
struct uart_port port;
int idx;
int ignore_rx;
struct rp2_card *card;
void __iomem *asic_base;
void __iomem *base;
void __iomem *ucode;
};
struct rp2_card {
struct pci_dev *pdev;
struct rp2_uart_port *ports;
int n_ports;
int initialized_ports;
int minor_start;
int smpte;
void __iomem *bar0;
void __iomem *bar1;
spinlock_t card_lock;
struct completion fw_loaded;
};
#define RP_ID(prod) PCI_VDEVICE(RP, (prod))
#define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
static inline void rp2_decode_cap(const struct pci_device_id *id,
int *ports, int *smpte)
{
*ports = id->driver_data >> 8;
*smpte = id->driver_data & 0xff;
}
static DEFINE_SPINLOCK(rp2_minor_lock);
static int rp2_minor_next;
static int rp2_alloc_ports(int n_ports)
{
int ret = -ENOSPC;
spin_lock(&rp2_minor_lock);
if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
/* sorry, no support for hot unplugging individual cards */
ret = rp2_minor_next;
rp2_minor_next += n_ports;
}
spin_unlock(&rp2_minor_lock);
return ret;
}
static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
{
return container_of(port, struct rp2_uart_port, port);
}
static void rp2_rmw(struct rp2_uart_port *up, int reg,
u32 clr_bits, u32 set_bits)
{
u32 tmp = readl(up->base + reg);
tmp &= ~clr_bits;
tmp |= set_bits;
writel(tmp, up->base + reg);
}
static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
{
rp2_rmw(up, reg, val, 0);
}
static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
{
rp2_rmw(up, reg, 0, val);
}
static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
int is_enabled)
{
unsigned long flags, irq_mask;
spin_lock_irqsave(&up->card->card_lock, flags);
irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
if (is_enabled)
irq_mask &= ~BIT(ch_num);
else
irq_mask |= BIT(ch_num);
writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
spin_unlock_irqrestore(&up->card->card_lock, flags);
}
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