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|
/*
* MPS2 UART driver
*
* Copyright (C) 2015 ARM Limited
*
* Author: Vladimir Murzin <vladimir.murzin@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* TODO: support for SysRq
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/tty_flip.h>
#include <linux/types.h>
#define SERIAL_NAME "ttyMPS"
#define DRIVER_NAME "mps2-uart"
#define MAKE_NAME(x) (DRIVER_NAME # x)
#define UARTn_DATA 0x00
#define UARTn_STATE 0x04
#define UARTn_STATE_TX_FULL BIT(0)
#define UARTn_STATE_RX_FULL BIT(1)
#define UARTn_STATE_TX_OVERRUN BIT(2)
#define UARTn_STATE_RX_OVERRUN BIT(3)
#define UARTn_CTRL 0x08
#define UARTn_CTRL_TX_ENABLE BIT(0)
#define UARTn_CTRL_RX_ENABLE BIT(1)
#define UARTn_CTRL_TX_INT_ENABLE BIT(2)
#define UARTn_CTRL_RX_INT_ENABLE BIT(3)
#define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4)
#define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5)
#define UARTn_INT 0x0c
#define UARTn_INT_TX BIT(0)
#define UARTn_INT_RX BIT(1)
#define UARTn_INT_TX_OVERRUN BIT(2)
#define UARTn_INT_RX_OVERRUN BIT(3)
#define UARTn_BAUDDIV 0x10
#define UARTn_BAUDDIV_MASK GENMASK(20, 0)
/*
* Helpers to make typical enable/disable operations more readable.
*/
#define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\
UARTn_CTRL_TX_INT_ENABLE |\
UARTn_CTRL_TX_OVERRUN_INT_ENABLE)
#define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\
UARTn_CTRL_RX_INT_ENABLE |\
UARTn_CTRL_RX_OVERRUN_INT_ENABLE)
#define MPS2_MAX_PORTS 3
struct mps2_uart_port {
struct uart_port port;
struct clk *clk;
unsigned int tx_irq;
unsigned int rx_irq;
};
static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port)
{
return container_of(port, struct mps2_uart_port, port);
}
static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off)
{
struct mps2_uart_port *mps_port = to_mps2_port(port);
writeb(val, mps_port->port.membase + off);
}
static u8 mps2_uart_read8(struct uart_port *port, unsigned int off)
{
struct mps2_uart_port *mps_port = to_mps2_port(port);
return readb(mps_port->port.membase + off);
}
static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off)
{
struct mps2_uart_port *mps_port = to_mps2_port(port);
writel_relaxed(val, mps_port->port.membase + off);
}
static unsigned int mps2_uart_tx_empty(struct uart_port *port)
{
u8 status = mps2_uart_read8(port, UARTn_STATE);
return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT;
}
static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
static unsigned int mps2_uart_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
}
static void mps2_uart_stop_tx(struct uart_port *port)
{
u8 control = mps2_uart_read8(port, UARTn_CTRL);
control &= ~UARTn_CTRL_TX_INT_ENABLE;
mps2_uart_write8(port, control, UARTn_CTRL);
}
static void mps2_uart_tx_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->state->xmit;
while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) {
if (port->x_char) {
mps2_uart_write8(port, port->x_char, UARTn_DATA);
port->x_char = 0;
port->icount.tx++;
continue;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
break;
mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA);
xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE;
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit))
mps2_uart_stop_tx(port);
}
static void mps2_uart_start_tx(struct uart_port *port)
{
u8 control = mps2_uart_read8(port, UARTn_CTRL);
control |= UARTn_CTRL_TX_INT_ENABLE;
mps2_uart_write8(port, control, UARTn_CTRL);
/*
* We've just unmasked the TX IRQ and now slow-starting via
* polling; if there is enough data to fill up the internal
* write buffer in one go, the TX IRQ should assert, at which
* point we switch to fully interrupt-driven TX.
*/
mps2_uart_tx_chars(port);
}
static void mps2_uart_stop_rx(struct uart_port *port)
{
u8 control = mps2_uart_read8(port, UARTn_CTRL);
control &= ~UARTn_CTRL_RX_GRP;
mps2_uart_write8(port, control, UARTn_CTRL);
}
static void mps2_uart_break_ctl(struct uart_port *port, int ctl)
{
}
static void mps2_uart_rx_chars(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) {
u8 rxdata = mps2_uart_read8(port, UARTn_DATA);
port->icount.rx++;
tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL);
}
tty_flip_buffer_push(tport);
}
static irqreturn_t mps2_uart_rxirq(int irq, void *data)
{
struct uart_port *port = data;
u8 irqflag = mps2_uart_read8(port, UARTn_INT);
if (unlikely(!(irqflag & UARTn_INT_RX)))
return IRQ_NONE;
spin_lock(&port->lock);
mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT);
mps2_uart_rx_chars(port);
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
static irqreturn_t mps2_uart_txirq(int irq, void *data)
{
struct uart_port *port = data;
u8 irqflag = mps2_uart_read8(port, UARTn_INT);
if (unlikely(!(irqflag & UARTn_INT_TX)))
return IRQ_NONE;
spin_lock(&port->lock);
mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT);
mps2_uart_tx_chars(port);
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
static irqreturn_t mps2_uart_oerrirq(int irq, void *data)
{
irqreturn_t handled = IRQ_NONE;
struct uart_port *port = data;
u8 irqflag = mps2_uart_read8(port, UARTn_INT);
spin_lock(&port->lock);
if (irqflag & UARTn_INT_RX_OVERRUN) {
struct tty_port *tport = &port->state->port;
mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT);
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
tty_flip_buffer_push(tport);
handled = IRQ_HANDLED;
}
/*
* It's never been seen in practice and it never *should* happen since
* we check if there is enough room in TX buffer before sending data.
* So we keep this check in case something suspicious has happened.
*/
if (irqflag & UARTn_INT_TX_OVERRUN) {
mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT);
handled = IRQ_HANDLED;
}
spin_unlock(&port->lock);
return handled;
}
static int mps2_uart_startup(struct uart_port
|